View PGA309_260856.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PGA309
SBOS292 - DECEMBER 2003
Voltage Output PROGRAMMABLE SENSOR CONDITIONER
FEATURES
D COMPLETE BRIDGE SENSOR CONDITIONER D VOLTAGE OUTPUT D D
- Ratiometric or Absolute DIGITALLY CALIBRATED - One-Wire and Two-Wire Digital Interface SENSOR ERROR COMPENSATION - Span - Offset - Temperature Drift of Span and Offset ELIMINATES POTENTIOMETERS ELIMINATES SENSOR TRIMS LOW, TIME-STABLE, TOTAL ADJUSTED ERROR SENSOR LINEARIZATION CIRCUITRY TEMPERATURE SENSE SELECT - Internal/External CALIBRATION TABLE LOOKUP LOGIC - Includes Linear Interpolation Algorithm NONVOLATILE CALIBRATION CONSTANTS - External 1K EEPROM (SOT23-5) SMALL TSSOP-16 PACKAGE -40C to +125C OPERATION +2.7V TO +5.5V OPERATION
+5V +5V VSD SDA Two- Wire EEPROM PRG SCL VOUT VEXC RISO 100 CL 10nF VSA REFIN/REFOUT Sensor Out GND VCC 1- Wire GND SDA SCL PGA309 PC Interface Board RS232
APPLICATIONS
D PRESSURE BRIDGE CONDITIONERS D D D D D D
- With Digital Calibration SENSORS REMOTE 4-20mA TRANSMITTERS WEIGH SCALE BRIDGE TRANSMITTERS SCADA REMOTE DATA ACQUISITION INDUSTRIAL PROCESS CONTROL AUTOMOTIVE SENSORS
D D D D D D D D D D
EVALUATION TOOLS
D HARDWARE DESIGNER'S KIT (PGA309DK) D
- Evaluate PGA309 and Sensor - Full Temperature Evaluation SOFTWARE CONTROL FOR DESIGNER'S KIT - Program PGA309 for Evaluation - Program PGA309 for First Production Run - Sensor Computation Analysis Tool
Power Supply +-
Easy- Use to- Calibration PC
+5V
PGA309
VIN2
VFB
RFB 100
Bridge Sensor
VIN1
VSJ
CF 150pF
TEMPIN
Test
GNDA
GNDD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
www.ti.com
PGA309
www.ti.com SBOS292 - DECEMBER 2003
PACKAGE/ORDERING INFORMATION(1)
PRODUCT PGA309 PACKAGE-LEAD TSSOP-16 PACKAGE DRAWING PW SPECIFIED TEMPERATURE RANGE -40C to +125C PACKAGE MARKING PGA309 ORDERING NUMBER PGA309AIPWR PGA309AIPWT TRANSPORT MEDIA, QUANTITY Tape and Reel, 2500 Tape and Reel, 250
(1) For the most current package and ordering information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range unless otherwise noted. Supply Voltage, VSD, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input Voltage, VIN1, VIN2(2) . . . . . . . . . . . . . . . . . . . . . -0.3V to VSA +0.3V Input Current, VFB, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Output Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -60C to +150C Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . -55C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C ESD Protection (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
DESCRIPTION
The PGA309 is a programmable analog signal conditioner designed for pressure bridge sensors. The analog signal path amplifies the sensor signal and provides digital calibration for zero, span, zero drift, span drift, and linearization errors. The calibration is done via a One-Wire digital serial interface or through a Two-Wire compatible connection. The calibration parameters are stored in external nonvolatile memory, to eliminate manual trimming and achieve long time stability. The all-analog signal path contains a 2X2 input mux, auto-zeroed programmable-gain instrumentation amplifier, linearization circuit, voltage reference, internal oscillator, control logic, and an output amplifier. Programmable level shifting compensates for sensor DC offsets. Automatic reset is initiated when supply is lost. The core of the PGA309 is the precision low-drift and low-noise front-end programmable gain amplifier (PGA). The overall gain of the PGA + output amplifier can be adjusted from +2.7V/V to +1152V/V. The polarity of the inputs can be switched through the Input multiplexer (mux) to accommodate sensors with unknown polarity output. The fault monitor circuit detects and signals sensor burnout, overload, and system fault conditions.
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
2
PGA309
www.ti.com SBOS292 - DECEMBER 2003
ELECTRICAL CHARACTERISTICS
BOLDFACE limits apply over the specified temperature range: TA = -40C to +125C
TA = +25C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER FRONT-END PGA + OUTPUT AMPLIFIER VOUT/VIN Differential Signal Gain Range(1) CONDITIONS Fine Gain Adjust = 1 Front-End PGA Gains: 4, 8, 16, 23, 27, 32, 42.67, 64, 128 Output Amplifier Gains: 2, 2.4, 3, 3.6, 4.5, 6, 9 VOUT/VIN Differential Gain = 8, RL = 5k || 200pF VOUT/VIN Differential Gain = 191, RL = 5k || 200pF VSA = VSD = VEXC = +5V MIN TYP 8 to 1152 MAX UNITS V/V
VOUT Slew Rate VOUT Settling Time (0.01%) VOUT Settling Time (0.01%) VOUT Nonlinearity External Sensor Output Sensitivity FRONT-END PGA Auto-Zero Internal Frequency Offset Voltage (RTI)(2) vs Temperature vs Supply Voltage, VSA vs Common-Mode Voltage Linear Input Voltage Range(3) Input Bias Current Input Impedance: Differential Input Impedance: Common-Mode Input Voltage Noise PGA Gain(1) Gain Range Steps Initial Gain Error
0.5 6 4.1 0.002 1 to 245 7 3 +0.2 2 1500/GF 0.2 0.1 30 || 6 50 || 20 4
V/s s s %FSR mV/V kHz V V/C V/V V/V V nA G || pF G || pF VPP V/V % % % ppm/C V kHz kHz
Coarse Offset Adjust Disabled
50
GF = Front-End PGA Gain
6000/GF VSA-1.5 1.5
0.1Hz to 10Hz, GF = 128 4, 8, 16, 23.27, 32, 42.67, 64, 128 GF = 4 to 42 GF = 64 GF = 128
vs Temperature Output Voltage Range Bandwidth COARSE OFFSET ADJUST (RTI OF FRONT-END PGA) Range vs Temperature Resolution FINE OFFSET ADJUST (ZERO DAC) (RTO of the Front-End PGA)(2) Programming Range Output Range Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Gain Error Drift Offset Offset Drift OUTPUT FINE GAIN ADJUST (GAIN DAC) Range Resolution Integral NonLinearity Differential NonLinearity
Gain = 4 Gain = 128
4 to 128 0.2 1 0.25 1.2 0.3 1.6 10 0.05 to VSA - 0.1 400 15.5
(15)(VREF/1250) 15 steps, 4-Bit + Sign
56
59.5 0.004 4
64
mV %/C mV
0 0.1 65,536 steps, 16-Bit DAC 73 20 0.5 0.1 10 5 10 0.33 to 1 10 20 0.5
VREF VSA-0.1
V V V LSB LSB % ppm/C mV V/C V/V V/V LSB LSB
65,536 steps, 16-Bit DAC
3
PGA309
www.ti.com SBOS292 - DECEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
BOLDFACE limits apply over the specified temperature range: TA = -40C to +125C
TA = +25C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER OUTPUT AMPLIFIER Offset Voltage (RTI of Output Amplifier)(2) vs Temperature vs Supply Voltage, VSA Common-Mode Input Range Input Bias Current Amplifier Internal Gain Gain Range Steps Initial Gain Error 3 5 30 0 100 2, 2.4, 3, 3.6, 4.5, 6, 9 2, 2.4, 3.6 4.5 6 9 2, 2.4, 3.6 4.5 6 9 RL = 10k 2 to 9 0.25 0.3 0.4 0.6 5 5 15 30 0.1 115 2 45 675 0.9708 0.9610 0.9394 0.9160 0.9102 0.7324 0.5528 +60 +0.37 0.0605 0.0547 0.0507 0.0449 0.0391 0.0352 0.0293 0.0254 -50 -0.15 VSA-1.2 or VEXC-100 100 VSA-0.12 VSA-0.12 VSA-1.2 20 VSA-1.5 mV V/C V/V V pA V/V % % % % ppm/C ppm/C ppm/C ppm/C V dB MHz Degrees CONDITIONS MIN TYP MAX UNITS
1 1.2 1.5 2.0
vs Temperature
Output Voltage Range(4) OpenLoop Gain Gain-Bandwidth Product Phase Margin Output Resistance OVER- AND UNDER-SCALE LIMITS Over-Scale Thresholds
4.9
Gain = 1 AC Small-Signal, Open-Loop, f = 1MHz (VREF = 4.096) Ratio of VREF, Register 5--Bits D5, D4, D3 = `000' Ratio of VREF, Register 5--Bits D5, D4, D3 = `001' Ratio of VREF, Register 5--Bits D5, D4, D3 = `010' Ratio of VREF, Register 5--Bits D5, D4, D3 = `011' Ratio of VREF, Register 5--Bits D5, D4, D3 = `100' Ratio of VREF, Register 5--Bits D5, D4, D3 = `101' Ratio of VREF, Register 5--Bits D5, D4, D3 = `110' +6 Ratio of VREF, Register 5--Bits D2, D1, D0 = `111' Ratio of VREF, Register 5--Bits D2, D1, D0 = `110' Ratio of VREF, Register 5--Bits D2, D1, D0 = `101' Ratio of VREF, Register 5--Bits D2, D1, D0 = `100' Ratio of VREF, Register 5--Bits D2, D1, D0 = `011' Ratio of VREF, Register 5--Bits D2, D1, D0 = `010' Ratio of VREF, Register 5--Bits D2, D1, D0 = `001' Ratio of VREF, Register 5--Bits D2, D1, D0 = `000' -7
Over-Scale Comparator Offset Over-Scale Comparator Offset Drift Under-Scale Thresholds
+114
mV mV/C
Under-Scale Comparator Offset Under-Scale Comparator Offset Drift FAULT MONITOR CIRCUIT INP_HI, INN_HI Comparator Threshold See Note 5
+93
mV mV/C V
INP_LO, INN_LO Comparator Threshold A1SAT_HI, A2SAT_HI Comparator Threshold A1SAT_LO, A2SAT_LO Comparator Threshold A3_VCM Comparator Threshold Comparator Hysteresis
40
mV V V V mV
4
PGA309
www.ti.com SBOS292 - DECEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
BOLDFACE limits apply over the specified temperature range: TA = -40C to +125C
TA = +25C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER INTERNAL VOLTAGE REFERENCE VREF1 VREF1 Drift vs Temperature VREF2 VREF2 Drift vs Temperature Input Current REFIN/REFOUT Output Current REFIN/REFOUT TEMPERATURE SENSE CIRCUITRY (ADC) Internal Temperature Measurement Accuracy Resolution Temperature Measurement Range Conversion Rate TEMPERATURE ADC External Temperature Mode Gain Range Steps Analog Input Voltage Range Temperature ADC Internal REF (2.048V) Full-Scale Input Voltage Differential Input Impedance Common-Mode Input Impedance Temp PGA + Temp ADC GPGA = 1, 2, 4, 8 GND-0.2 Register 6, Bit D8 = 1 (+Input) - (-Input)
GPGA GPGA GPGA GPGA =1 =2 =4 =8
CONDITIONS
MIN
TYP
MAX
UNITS
Register 3, Bit D9 = 1 Register 3, Bit D9 = 0 Internal VREF Disabled VSA > 2.7V for VREF = 2.5V VSA > 4.3V for VREF = 4.096V Register 6, Bit D9 = 1 12-Bit + Sign, Two's Complement Data Format
2.46 4.0
2.5 +10 4.096 +10 100 1 1
2.53 4.14
V ppm/C V ppm/C A mA mA
2 0.0625 -55 +150 24
R1, R0 = `11', 12-Bit + Sign Resolution
C C C ms
1 to 8 VSA+0.2 2.048/GPGA 2.8/GPGA 3.5 3.5 1.8 0.9 11 13 14 15 0.004 1.2 0.7 0.5 0.4 1.2 0.6 0.3 0.3 800 400 200 150 0.05 5 80 105 100
V/V V V M M M M M Bits + Sign Bits + Sign Bits + Sign Bits + Sign % mV mV mV mV V/C V/C V/C V/C V/V V/V V/V V/V % ppm/C ppm/V dB dB
Resolution
R1, R0 = `00', ADC2X = `0', Conversion Time = 8ms R1, R0 = `01', ADC2X = `0', Conversion Time = 32ms R1, R0 = `10', ADC2X = `0', Conversion Time = 64ms R1, R0 = `11', ADC2X = `0', Conversion Time = 128ms
GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA =1 =2 =4 =8 =1 =2 =4 =8 =1 =2 =4 =8
Integral Nonlinearity Offset Error
Offset Drift
Offset vs VSA
Gain Error Gain Error Drift Gain vs VSA Common-Mode Rejection
0.50 50
At DC and GPGA = 8 At DC and GPGA = 1
5
PGA309
www.ti.com SBOS292 - DECEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
BOLDFACE limits apply over the specified temperature range: TA = -40C to +125C
TA = +25C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER TEMPERATURE ADC (CONTINUED) Temp ADC Ext. REF (VREFT = VREF, VEXC, or VSA) Full-Scale Input Voltage Differential Input Impedance Common-Mode Input Impedance Register 6, Bit D8 = 0 (+Input) - (-Input)
GPGA GPGA GPGA GPGA =1 =2 =4 =8
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
R1, R0 = `00', ADC2X = `0', Conversion Time = 6ms R1, R0 = `01', ADC2X = `0', Conversion Time = 24ms R1, R0 = `10', ADC2X = `0', Conversion Time = 50ms R1, R0 = `11', ADC2X = `0', Conversion Time = 100ms
GPGA GPGA GPGA GPGA GPGA GPGA GPGA GPGA =1 =2 =4 =8 =1 =2 =4 =8
Integral Nonlinearity Offset Error
Offset Drift
Gain Error Gain Error Drift Gain vs VSA Common-Mode Rejection External Temperature Current Excitation Current Excitation Temperature Drift Voltage Compliance Range 1 Linearization DAC Range Linearization DAC Resolution VEXC Gain Gain Error Drift Range 2 Linearization DAC Range Linearization DAC Resolution VEXC Gain Gain Error Drift VEXC Range Upper Limit IEXC SHORT DIGITAL INTERFACE Two-Wire Compatible One-Wire Maximum Lookup Table Size(6) Two-Wire Data Rate LOGIC LEVELS Input Levels (SDA, SCL, PRG) ITEMP
At DC and GPGA = 8 At DC and GPGA = 1 Register 6, Bit D11 = 1 5.8
VREFT/GPGA 2.4/GPGA 8 8 8 8 11 13 14 15 0.01 2.5 1.25 0.7 0.3 1.5 1.0 0.7 0.6 -0.2 2 80 100 85 7 5 VSA-1.2 8
V M M M M M Bits + Sign Bits + Sign Bits + Sign Bits + Sign % mV mV mV mV V/C V/C V/C V/C % ppm/C ppm/V dB dB A nA/C V
LINEARIZATION ADJUST AND EXCITATION VOLTAGE (VEXC) Register 3, Bit D11 = 0 With Respect to VFB 128 Steps, 7-Bit + Sign With Respect to VREF Register 3, Bit D11 = 1 With Respect to VFB 128 Steps, 7-Bit + Sign With Respect to VREF IEXC = 5mA Short-Circuit VEXC Output Current Bus Speed Serial Speed Baud Rate Communication Between PGA309 and EEPROM Low High Hysteresis Open Drain w/90A Internal Pull-Up to VSD, ISINK = 5mA Open Drain, ISINK = 5mA 1 4.8K 17 x 3 x 16 65 0.2 * VSD 0.1 * VSD 0.4 0.4 -0.166 to +0.166 1.3 0.83 25 -0.124 to +0.124 0.969 0.52 25 VSA - 0.5 50 400 38.4K V/V mV/V V/V ppm/C V/V mV/V V/V ppm/C V mA kHz Bits/s Bits kHz V V V V V
0.7 * VSD
Output LOW Level (SDA, SCL) Output LOW Level (PRG)
6
PGA309
www.ti.com SBOS292 - DECEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
BOLDFACE limits apply over the specified temperature range: TA = -40C to +125C
TA = +25C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER POWER SUPPLY VSA, VSD ISA + ISD, Quiescent Current POWER-ON RESET Power-Up Threshold Power-Down Threshold TEMPERATURE RANGE Specified Performance Operational - Degraded Performance -40 -55 +125 +150 C C VSA Rising VSA Falling 2.2 1.7 2.7 V V 2.7 VSA = VSD = +5V, without Bridge Load 1.2 5.5 1.6 V mA CONDITIONS MIN TYP MAX UNITS
(1) PGA309 total differential gain from input (VIN1-VIN2) to output (VOUT). VOUT / (VIN1-VIN2) = (PGA front-end gain) (output amplifier gain) (fine gain adjust). (2) RTI = referred to input. RTO = referred to output. (3) Linear input range is the allowed min/max voltage on the VIN1 and VIN2 pins for the input PGA to continue to operate in a linear region. The allowed common-mode and differential voltage is dependent upon gain and offset settings. Refer to the Gain Scaling section for more information. (4) Unless limited by over/under-scale setting. (5) When VEXC is enabled, a minimum reference selector circuit becomes the reference for the comparator threshold. This minimum reference selector circuit uses VEXC - 100mV and VSA - 1.2V and compares the VINX pin to the lower of the two references. This ensures accurate fault monitoring in conditions where VEXC might be higher or lower than the input CMR of the PGA input amplifier relative to VSA. (6) Lookup Table allows multislope compensation over temperature. Lookup Table has access to 17 calibration points consisting of 3 adjustment values (Tx, Temperature, ZMx, Zero DAC, GMx, Gain) that are stored in 16-bit data format (17x3x16 = Lookup Table size).
7
PGA309
www.ti.com SBOS292 - DECEMBER 2003
PIN CONFIGURATION
Top View VEXC GNDA VSA VIN1 VIN2 VFB VOUT VSJ 1 2 3 4 PGA309 5 6 7 8 12 PRG 11 GNDD 10 VSD 9 TEST 16 REFIN/REFOUT 15 TEMPIN 14 SDA 13 SCL TSSOP
PIN DESCRIPTION
PIN 1 2 3 4 5 6
NAME
VEXC GNDA VSA VIN1 VIN2 VFB
DESCRIPTION
Bridge sensor excitation. Connect to bridge if linearization and/or internal reference for bridge excitation is to be used. Analog ground. Connect to analog ground return path for VSA. Should be same as GNDD. Analog voltage supply. Connect to analog voltage supply. To be within 200mV of VSD. Signal input voltage 1. Connect to + or - output of sensor bridge. Internal multiplexer can change connection internally to front-end PGA. Signal input voltage 2. Connect to + or - output of sensor bridge. Internal multiplexer can change connection internally to front-end PGA. VOUT feedback pin. Voltage feedback sense point for over/under-scale limit circuitry. When internal gain set resistors for the output amplifier are used, this is also the voltage feedback sense point for the output amplifier. VFB in combination with VSJ allows for ease of external filter and protection circuits without degrading the PGA309 VOUT accuracy. VFB must always be connected to either VOUT or the point of feedback for VOUT, if external protection is used. Analog output voltage of conditioned sensor. Output amplifier summing junction. Use for output amplifier compensation when driving large capacitive loads (> 100pF) and/or for using external gain setting resistors for the output amplifier. Test/External Controller Mode pin. Pull to GNDD in normal mode. Digital voltage supply. Connect to digital voltage supply. To be within 200mV of VSA. Digital ground. Connect to digital ground return path for VSD. Should be same as GNDA. Single-wire interface program pin. UART-type interface for digital calibration of the PGA309 over a single wire. Can be connected to VOUT for a three-lead (VS, GND, VOUT) smart programmable sensor assembly. Clock input/output for Two-Wire, industry-standard compatible interface for reading digital calibration and configuration from external EEPROM. Can also communicate directly to the registers in the PGA309 through the Two-Wire, industry-standard compatible interface. Data input/output for Two-Wire, industry-standard compatible interface for reading digital calibration and configuration from external EEPROM. Can also communicate directly to the registers in the PGA309 through the Two-Wire, industry-standard compatible interface. External temperature signal input. PGA309 can be configured to read a bridge current sense resistor as an indicator of bridge temperature, or an external temperature sensing device such as diode junction, or RTD, or thermistor. This input can be gained up internally by X1, X2, X4, or X8. In addition, this input can be read differentially with respect to VGNDA, VEXC, or the internal VREF. There is also an internal, register-selectable, 7A current source (ITEMP) that can be connected to TEMPIN as an RTD, thermistor, or diode excitation source. Reference input/output pin. As an output, the internal reference (selectable as 2.5V or 4.096V) is available for system use on this pin. As an input, the internal reference may be disabled and an external reference can then be applied as the reference for the PGA309.
7 8 9 10 11 12 13
VOUT VSJ TEST VSD GNDD PRG SCL
14
SDA
15
TEMPIN
16
REFIN/REFOUT
8
PGA309
www.ti.com SBOS292 - DECEMBER 2003
TYPICAL CHARACTERISTICS
TA = +25C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. VREF vs TEMPERATURE IB CURRENT vs TEMPERATURE
4.090 4.085 4.080 VREF (V)
1.0 0.5 0 IB (nA) -0.5 -1.0 -1.5 -2.0
Average, nA
4.075 Average 4.070 4.065 4.060 -55 -35 -15
-2.5 -3.0 -55 -35 -15 5 25 45 65 85 105 125 145
5
25
45
65
85
105 125 145
Temperature (_C)
Temperature (_C)
9 8
I TEMP CURRENT vs TEMPERATURE 70 60 Average 50 40 CMRR (dB) 30 20 10 0 -10 -20 5 25 45 65 85 105 125 145 -30
COMMON-MODE REJECTION RATIO vs FREQUENCY RTO of Front-End PGA
7 6 ITEMP (A) 5 4 3 2 1 0 -55 -35 -15
10
100
1k
10k
100k
1M
Temperature (_C)
Frequency (Hz)
POWER-SUPPLY REJECTION RATIO vs FREQUENCY 90 80 70 60 PSRR (dB) 50 40 30 20 10 0 -10 10 Small-Signal VREF and VEXT Enabled VREF = 2.5V PSRR at VOUT 100 1k 10k 100k 1M Gain (dB) 60 80
CLOSED-LOOP GAIN vs FREQUENCY GOUTAMP = Output Amplifer Gain GOUTAMP = 9V/V GFRONT = 128V/V
40
GOUTAMP = 9V/V GFRONT = 32V/V
20
GOUTAMP = 2V/V GFRONT = 8V/V
0 10 100 1k Frequency (Hz)
GOUTAMP = 2V/V GFRONT = 32V/V 10k 100k 1M
Frequency (Hz)
9
PGA309
www.ti.com SBOS292 - DECEMBER 2003
TYPICAL CHARACTERISTICS (Cont.)
TA = +25C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. VOUT SWING TO RAIL vs ILOAD AT TROOM VS VS - 0.1 VS - 0.2 VS - 0.3 VS - 0.4 VS - 0.5 0.5 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 ILOAD (mA) VS = 2.7V VS = 5V 0.4 0.2 0 -55 -35 -15 VS = 2.7V VS = 5V IQ (mA) IQ vs TEMPERATURE
1.6 1.4 1.2 1.0 0.8 0.6
All Blocks Enabled
Ref, Exc, and ADC Disabled
5
25
45
65
85
105 125 145
Temperature (_C)
TEMPERATURE ADC INTERNAL MODE 0.4 0.2 Temp ADC Error (_C) Total Error (% of FS) 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -55 -35 -15 5 25 45 65 85 105 125 145 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
TEMPERATURE ADC EXTERNAL MODES Reg 6 = 0433h VREF = 2.5V On-Chip Reg 6 = 0503h VREF = 2.048V ADC-Down
Reg 6 = 0430h VREF = 2.5V Reg 6 = 0403h VREF = 5V External 0 20 40 60 80 100
-0.4 -100 -80 -60 -40 -20
Actual Die Temperature (_ C)
Input Signal (% FS of a given reference)
0.1Hz TO 10Hz VREF NOISE VREF = 4.096V
PGA VOUT OUTPUT 0.1Hz TO 10Hz PEAK-TO-PEAK NOISE G = 1152
50V/div
1mV/div
1s/div
1s/div
10
PGA309
www.ti.com SBOS292 - DECEMBER 2003
TYPICAL CHARACTERISTICS (Cont.)
TA = +25C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. LARGE-SIGNAL STEP RESPONSE Gain = 8 LARGE-SIGNAL STEP RESPONSE Gain = 1152
VOUT (500mV/div)
Time (10s/div)
VOUT (500mV/div)
Time (10s/div)
SMALL-SIGNAL STEP RESPONSE Gain = 8
SMALL-SIGNAL STEP RESPONSE Gain = 256
VOUT (50mV/div)
Time (10s/div)
VOUT (50mV/div)
Time (10s/div)
CAPACITIVE LOAD DRIVE 25
OVERVOLTAGE RECOVERY VOUT
0.5% Settling Time (s)
20
15 GOUTAMP = 9V/V GOUTAMP = 3.6V/V
VIN (200mV/div), VOUT (1V/div)
GOUTAMP = 2V/V
10
VIN
5
0 0 500 1000 1500 2000 2500 Time (100s/div) CLOAD (pF)
11
PGA309
www.ti.com SBOS292 - DECEMBER 2003
FUNCTIONAL DESCRIPTION
The PGA309 is a smart programmable analog signal conditioner designed for resistive bridge sensor applications. It is a complete signal conditioner with bridge excitation, initial span and offset adjustment, temperature adjustment of span and offset, internal/external temperature measurement capability, output over-scale and under-scale limiting, fault detection, and digital calibration. The PGA309, in a calibrated sensor module, can reduce errors to the level approaching the bridge sensor repeatability. Figure 1 shows a block diagram of the PGA309. Following is a brief overview of each major function. SENSOR ERROR ADJUSTMENT RANGE The adjustment capability of the PGA309 summarized in Table 1.
FSS (full-scale sensitivity) Span TC Span TC nonlinearity Zero offset Zero offset TC Zero offset TC nonlinearity Sensor impedance 1mV/V to 245mV/V Over 3300ppmFS/C(1) > 10% 200%FS(2) Over 3000ppmFS/C(2) > 10% Down to 200(3)
order to compensate for second-order drift nonlinearity, the span drift can be fitted to piecewise linear curves during calibration with the coefficients stored in an external nonvolatile EEPROM lookup table. Following the fine gain adjust stage is the output amplifier that provides additional programmable gain. Two key output amplifier connections, VFB and VSJ, are brought out on the PGA309 for application flexibility. These connections allow for an accurate conditioned signal voltage while also providing a means for PGA309 output overvoltage and large capacitive loads for RFI/EMI filtering required in many end applications. OFFSET ADJUSTMENT The sensor offset adjustment is performed in two stages. The input referred Coarse Offset Adjust DAC has approximately a 60mV offset adjustment range for a selected VREF of 5V. The fine offset and the offset drift are canceled by the 16-bit Zero DAC that sums the signal with the output of the front-end instrumentation amplifier. Similar to the Gain DAC, the input digital values of the Zero DAC are controlled by the data in the Temperature Compensation Lookup Table, stored in external EEPROM, driven by the Temp ADC. The range of the Zero DAC is 0 to VREF. VOLTAGE REFERENCE The PGA309 contains a precision low-drift voltage reference (selectable for 2.5V or 4.096V) that can be used for external circuitry through the REFIN/REFOUT pin. This same reference is used for the Coarse Offset Adjust DAC, Zero DAC, over/under-scale limits and sensor excitation and linearization through the VEXC pin. When the internal reference is disabled, the REFIN/REFOUT pin should be connected to an external reference or to VSA for ratiometric-scaled systems. SENSOR EXCITATION AND LINEARIZATION A dedicated circuit with a 7-bit + sign DAC for sensor voltage excitation and linearization is provided on the PGA309. This block scales the reference voltage and sums it with a portion of the PGA309 output to compensate the positive or negative bow-shaped nonlinearity exhibited by many sensors over their applied pressure range. Sensors not requiring linearization can be connected directly to the supply (VSA) or the voltage reference pin (REFIN/REFOUT).
is
(1) Depends on the temperature sensing scheme (2) Combined coarse and fine offset adjust (3) Lower impedance possible by using a dropping resistor in series with the bridge
Table 1. PGA309 Adjustment Capability GAIN SCALING The core of the PGA309 is the precision low-drift and no 1/f noise front-end PGA. The overall gain of the front-end PGA + Output Amplifier can be adjusted from 2.7V/V to 1152V/V. The polarity of the inputs can be switched through the 2X2 input mux to accommodate sensors with unknown polarity output. The front-end PGA provides initial coarse signal gain using a no 1/f noise, auto-zero instrumentation amplifier. The fine gain adjust is accomplished by the 16-bit attenuating gain digital-to-analog converter (DAC). The Gain DAC is controlled by the data in the Temperature Compensation Lookup Table driven by the temperature analog-to-digital converter (Temp ADC). In
12
PGA309
www.ti.com SBOS292 - DECEMBER 2003
+5V
VSD
V SA
REFIN /REFOU T
PGA309
VREF Power-On Reset Band-Gap Voltage Reference VLIN Linearization DAC VFB /10 SDA Interface and Control Circuitry VTE MP TEMPIN Temp ADC Signals Mux SCL Two-Wire EEPROM (SOT23- 5) +5V
VEXC
VO UT
Temperature ADC
Temperature ADC Input Select
Coarse Offset Adjust
SpanTC and OffsetTC Adjust Lookup Table with interpolation
PRG
Fine Offset Adjust V OS Zero DAC
VOU T
VIN1 2x2 Multiplexer Front- End PGA Out
Over/Under- Scale Limits Fault Out VOU T F IL T Gain DAC Fine Gain Adjust R ISO 100
Front-End PGA (Gain X4 to X128)
Bridge Sensor
VIN2
Output Amp
V OUT
CL 10nF Int/Ext Feedback VF B RF B 100
RT EMP
Fault Conditions Monitoring Circuit
Fault Out
Test
V FB Test Logic Output Coarse Gain Adjust (X2 to X9) V SJ
CF 150pF
GND A
GNDD
Figure 1. Simplified Diagram of the PGA309
13
PGA309
www.ti.com SBOS292 - DECEMBER 2003
ADC FOR TEMPERATURE SENSING The compensation for the sensor span and offset drifts is driven by the temperature sense circuitry. Either internal or external temperature sensing is possible. The temperature can be sensed in one of the following ways: D Bridge impedance change (excitation current sense, in the positive or negative part of the bridge), for sensors with large temperature coefficient of resistance (TCR > 0.1%/C) D On-chip PGA309 temperature, when the chip is located sufficiently close to the sensor D External diode, thermistor, or RTD placed on the sensor membrane. The temperature signal is digitized by the onboard Temp ADC. The output of the Temp ADC is used by the control digital circuit to pull the data from the Lookup Table in an external EEPROM, and set the output of the Gain DAC and the Zero DAC to the calibrated values as temperature changes. An additional function provided through the Temp ADC is the ability to read the VOUT pin back through the Temp ADC input mux. This provides flexibility for a digital output through either One-Wire or Two-Wire interface, as well as the possibility for an external microcontroller to perform real-time custom calibration of the PGA309. EXTERNAL EEPROM AND TEMPERATURE COEFFICIENTS The PGA309 uses an industry-standard Two-Wire external 256 to 1K-bit EEPROM (typically, a SOT23-5 package). The PGA309 has been tested to operate with EEPROM parts Microchip 24LCxx and 24AAxx. The first part of the external EEPROM contains the configuration data for the PGA309, with settings for: D Register 3--Reference Control and Linearization D Register 4--PGA Coarse Offset and Gain/Output Amplifier Gain D Register 5--PGA Configuration and Over/UnderScale Limit D Register 6--Temp ADC Control This section of the EEPROM contains its own individual checksum (Checksum1). The second part of the external EEPROM contains up to 17 temperature index values and corresponding temperature coefficients for the Zero DAC and Gain DAC adjustments with measured temperature and contains its own checksum (Checksum2). The PGA309 lookup logic contains a linear interpolation algorithm for accurate DAC adjustments between stored temperature indexes. This approach allows for a piecewise linear temperature compensation of up to 17 temperature indexes and associated temperature coefficients.
14
If either Checksum1, Checksum2, or both are incorrect, the output of the PGA309 is set to high-impedance. FAULT MONITOR To detect sensor burnout or short, a set of four comparators are connected to the inputs of the front-end PGA. If any of the inputs are taken to within 40mV of ground or VEXC, or violate the input CMR of the front-end PGA, then the corresponding comparator sets a sensor fault flag that causes the PGA309 VOUT to be driven within 100mV of either VSA or ground, depending upon the alarm configuration setting (Register 5--PGA Configuration and Over/UnderScale Limit). This will be well above the set over-scale limit level or well below the set under-scale limit level. The state of the fault condition can be read in digital form in Register 8--Alarm Status Register. If the over/under-scale limiting is disabled, the PGA309 output voltage will still be driven within 100mV of either VSA or ground, depending upon the alarm configuration setting. There are five other fault detect comparators that help detect subtle PGA309 front-end violations that could result in linear voltages at VOUT and be interpreted as valid states. These are especially useful during factory calibration and setup and are configured through Register 5--PGA Configuration and Over/Under-Scale Limit. Their status can also be read back through Register 8--Alarm Status Register. OVER-SCALE AND UNDER-SCALE LIMITS The over-scale and under-scale limit circuitry combined with the fault monitor circuitry provides a means for system diagnostics. A typical sensor-conditioned output may be scaled for 10% to 90% of the system ADC range for the sensor normal operating range. If the conditioned pressure sensor is below 4%, it is considered under-pressure; if over 96%, it is considered over-pressure. The PGA309 over/under-scale limit circuit can be programmed individually for under-scale and over-scale that clip or limit the PGA309 output. From a system diagnostic view, it is known that 10% to 90% of ADC range is normal operation, < 4% is under-pressure, and > 96% is over-pressure. If the fault detect circuitry is used, a detected fault will cause the PGA309 output to be driven to positive or negative saturation. If this fault flag is programmed for high, then > 97% ADC range will be a fault; if programmed for low, then < 3% ADC range will be a fault. Now the system software can be used to distinguish between over- or under-pressure condition, which indicates an out-of-control process, and a sensor fault.
PGA309
www.ti.com SBOS292 - DECEMBER 2003
POWER-UP AND NORMAL OPERATION The PGA309 has circuitry to detect when the power supply is applied to the PGA309, and reset the internal registers and circuitry to an initial state. This reset also occurs when the supply is detected to be invalid, so that the PGA309 is in a known state when the supply becomes valid again. The threshold for this circuit is approximately +1.5V to +2.5V. After the power supply becomes valid, the PGA309 waits for approximately 25ms and then attempts to read the configuration data from the external EEPROM device. If the EEPROM has the proper flag set in address location 0 and 1, then the PGA309 continues reading the EEPROM, otherwise, the PGA309 waits for one second before trying again. If the PGA309 detects no response from the EEPROM, the PGA309 waits for one second and tries again; otherwise, the PGA309 tries to free the bus and waits for 25ms before trying to read the EEPROM again. If successful (including valid checksum data), the PGA309 triggers the Temp ADC to measure temperature. For 16-bit resolution results the converter takes approximately 125ms to complete a conversion. Once the conversion is complete, the PGA309 begins reading the Lookup Table information from the EEPROM to calculate the settings for the Gain DAC and Zero DAC. The PGA309 reads the entire Lookup Table so that it can determine if the checksum for the Lookup Table is correct. Each entry in the Lookup Table requires approximately 500s to read from the EEPROM. Once the checksum is determined to be valid, the calculated values for the Gain and Zero DACs are updated into their respective registers, and the output amplifier is enabled. The PGA309 then begins looping through this entire procedure, starting with reading the EEPROM configuration registers, then starting a new conversion on the Temp ADC, which then triggers reading the Lookup Table data from the EEPROM. This loop continues indefinitely.
DIGITAL INTERFACE There are two digital interfaces on the PGA309. The PRG pin uses a One-Wire, UART-compatible interface with bit rates from 4.8Kbits/s to 38.4Kbits/s. The SDA and SCL pins together form an industry standard Two-Wire interface at clock rates from 1kHz to 400kHz. The external EEPROM uses the Two-Wire interface. Communication to the PGA309 internal registers, as well as to the external EEPROM, for programming and readback can be conducted through either digital interface. It is also possible to connect the One-Wire communication pin, PRG, to the VOUT pin in true three-wire sensor modules and still allow for programming. In this mode, the PGA309 output amplifier may be enabled for a set time period and then disabled again to allow sharing of the PRG pin with the VOUT connection. This allows for both digital calibration and analog readback during sensor calibration in a three-wire sensor module. The Two-Wire interface has timeout mechanisms to prevent bus lockup from occurring. The Two-Wire master controller in the PGA309 has a mode that attempts to free up a stuck-at-zero SDA line by issuing SCL pulses, even when the bus is not indicated as idle after the timeout period has expired. The timeout will only apply when the master portion of the PGA309 is attempting to initiate a Two-Wire communication.
15
PGA309
www.ti.com SBOS292 - DECEMBER 2003
DETAILED DESCRIPTION
GAIN SCALING The PGA309 contains three main gain blocks for scaling differential input bridge sensor signals, as shown in Figure 2. The front-end PGA contains the highest gain selection to allow for the highest signal-to-noise ratio by applying the largest gain at the front of the signal chain before the addition of other noise sources. The Front-end PGA gain select has eight settings (x4, x8, x16, x23.27, x32, x42.67, x64, x128) and is set by Register 4 bits (11:8). Bit 11 selects the polarity of the input mux. The front-end PGA is followed by the Gain DAC. The fine gain adjust is controlled by the 16-bit Gain DAC and is adjustable from x0.3333 to x1. Register 2 is used only for the Gain DAC setting. Final signal gain is applied through the output amplifier, which has an internal gain select of seven settings (x2, x2.4, x3, x3.6, x4.5, x6, x9). The output amplifier has a selection to disable the internal gain and allow user-supplied external resistors to set the output amplifier
Example: Solving for Gain Settings An example bridge sensor application will be used to examine internal nodes of the PGA309 that are related to the gain blocks (refer to Figure 3 and Figure 4). Given: FSS = 20mV/V VOS =0mV VREF = +5V VEXC = +5V VSA = +5V RBRG = 2k VOUTMIN = +0.5V VOUTMIAX= +4.5V 4. Find: Front-End PGA Gain Gain DAC Setting Zero DAC Setting Over Amplifier Gain
gain. Register 4 bits (14:12) select the internal output amplifier gains, except when programmed with `111' when the internal feedback is disabled. The combined gain blocks allow for a VOUT/VDIFF signal gain of x2.666 (400kHz bandwidth) to x1152 (15.5kHz bandwidth).
PGA309 Differential Gain Range X2.6666 to X1152 Zero DAC VIN2 VDIFF VIN1 Input Mux VINN VINP VOUT Gain Network
Front-End PGA X4, X8, X16, Output Amplifier Fine Gain Adjust X2, X2.4, X3, X3.6, X23.27, X0.3333 to X1 X4.5, X6, X9 X32, X42.67, X64, X128 16-Bit Resolution
Figure 2. Gain Blocks of the PGA309
Solution: 1. Maximum Sensor Output: VBRmax = (FSS)(VEXC) VBRmax = (20mV/V)(5V) = 100mV Total Gain: GT = (VOUTMAX - VOUTMIN)(VBRmax) GT = (4.5V - 0.5V)(100mV) = 40 Partition the Gain: Front-End PGA Gain = X23.27 Output Amplifier Gain = X2 Fine Gain (Gain DAC) = X0.859475719 GT = (Front-End PGA Gain)(Fine Gain)(Output Amp Gain) GT = (23.27)(0.859475719)(2) = 40 Calculate exact DAC Gain value: 1LSB = (1.000000000 - 0.333333333)/65536 = 1.0172526 x 10-5V/V Decimal # counts = (Desired Gain - 0.333333333)/(1.0172526 x 10-5) Decimal # counts = (0.859475719 - 0.333333333)/(1LSB) = 51,721.90133
Calculate exact DAC Gain value, continued: Use 51,722 counts 0xCA0A1100 1010 0000 1010 X0.859475571 Calculate Zero DAC value: VZERO DAC = (VOUTMIN)/[(Gain DAC)(Output Amplifier Gain)] VZERO DAC = (0.5V)/[(X0.859475571)(2)] = 0.29087505V Decimal # counts = VZERO DAC/(VREF/65536) Decimal # counts = 0.29087505/(5/65536) = 3812.55746 Use 3813 counts 0x0EE50000 1110 1110 0101 0.290908813V Calculate VCM and VDIFF for Maximum Sensor Output (see Figure 3): VDIFF = VINP - VINN VDIFF = 2.550 - 2.450 = 100mV VCM = (VINP + VINN)/2 VCM = (2.550V + 2.450V)/2 = 2.5V
5.
2.
3.
4.
6.
16
PGA309
www.ti.com SBOS292 - DECEMBER 2003
The front-end PGA of the PGA309 is a three op amp instrumentation amplifier for optimum rejection of common-mode voltages. This instrumentation amplifier is constructed using op amps with auto-zero front-ends to virtually eliminate 1/f noise. As with any instrumentation amplifier there are limitations on the output voltage swing and input commonmode voltage range. The circuit in Figure 3 is representative of the front-end PGA inside of the PGA309 and is used to evaluate critical internal node voltages to ensure that output voltage swing and common-mode limits are not violated. It is possible to violate the limits of these internal nodes and still have apparently valid output voltages at VOUT of the PGA309. There are internal comparators that can be set to monitor these internal nodes to indicate an out-of-limit condition during sensor calibration (see Fault Monitor section). After appropriate scaling for the PGA309 gain blocks are chosen, a simple hand analysis can check for internal node limit violations. It is key to convert the input voltages to the PGA309 (VINP, VINN) to common-mode and differential components for the maximum sensor
output, VBRmax. The model for this conversion is illustrated in Figure 3. The front-end PGA must have a gain of 4 in difference amplifier A3. To analyze important internal nodes VOA1 and VOA2, it is necessary to assign the proper gain factor (G) to op amps A1 and A2. This is detailed in Figure 3 with the respective equations for the output voltages shown at the appropriate nodes. For VBRmax, VOA1 and VOA2 are within the allowed voltage swing of: 0.1V < (VOA1 or VOA2) < VS - 0.12 Or for this example: 0.1V < (VOA1 or VOA2) < 4.88V Other applications may yield different results that require different gain scaling or a resistor in the positive or negative leg of the sensor excitation path to adjust the common-mode input voltage of the PGA309. The input voltage range of the PGA309 is specified as 0.2V < IVR < VSA - 1.5V, which for this application translates to 0.2V < IVR < 3.5V. In Figure 3 we see VINP = 2.550V and VINN = 2.450V, which is within the acceptable input voltage range specification.
+5V
2.04k
1.96k
V DIFF = V INP - V INN V DIFF = 2.550V - 2.450V V DIFF = 100mV
V CM = (V INP + V INN)/2 V CM = (2.550V - 2.450V)/2 V CM = 2.5V
V ZERO DAC = 0.290875V ZeroDAC = 3813 counts (V REF = +5V) V FRONT/V DIFF = X23.27 G = X5.8175 +5V V REF FRONT-END PGA GAINS V FRONT/V DIFF G = 1 + 2 R F /R G X4 X8 X16 X23.27 X32 X42.67 X64 X128 X1 X2 X4 X5.8175 X8 X10.6675 X16 X32
2.550V 1.96k 2.04k 2.450V 0.1V < V O A 2 < V S - 0.12 V V OA2 = V CM + G(V DIFF/2) V INP V ZERO DAC
16- Bit DAC Z ero DAC
2.55V
A2 R Auto- Zero
4R
V DIFF/2 50mV Front- End PGA Gain V CM 2.5V RG
RF
PGA Difference Amplifier A3 Auto- Zero V FRONT 2.327V + 0.290875V = 2.617875V
RF
V DIFF/2 50mV 2.45V V INN
A1 Auto- Zero
R
4R (2)
Input Mux (1)
V OA1 = V CM - G(V DIFF/2) 0.1V < V OA1 < V S - 0.12V NOTES: (1) Input mux allows for sensor output polarity reversal. (2) PGA difference amplifier gain of X4 allows full range out of Z ero DAC and full voltage swing out of A1 and A2 without common- mode violation on A3 input.
Figure 3. Front-End PGA Gain
17
PGA309
www.ti.com SBOS292 - DECEMBER 2003
The output (VFRONT) of difference amplifier A3 has a gain of 4 in it for voltages out of A2 and A1, but a gain of 1 for voltages out of the Zero DAC. VFRONT is shown with the contribution from VDIFF times the front-end PGA gain plus the Zero DAC output voltage. The VFRONT signal is further processed through the Gain DAC and output amplifier gain blocks. Figure 4 depicts the Gain DAC and Output Amplifier gain blocks inside the PGA309. For this example the Gain DAC was set to x0.859475571 and the output amplifer to X2. As shown in Figure 4, the net output voltage, VOUT, is 4.5V for the maximum sensor output, VBRmax. For the sensor output of zero volts:
VOUTMIN = VZERO DAC [(Gain DAC)(Output Amplifier Gain)]
OFFSET SCALING The coarse offset adjust is implemented before the front-end PGA gain to allow for maximum dynamic range. Many bridge sensors have initial offsets comparable to their maximum scale outputs. The coarse offset adjust can be applied as positive or negative. It is implemented in a 4-bit DAC + sign and contains 14 positive selections, 14 negative selections, and zero. The resolution in either the positive or negative range is VREF/1200. For a +5V reference, this translates to 4.2mV steps. Figure 5 depicts the PGA309 with the gain settings used for the example bridge sensor application detailed in the Gain Scaling section. The conversion of the bridge initial differential offset plus its common-mode to the differential plus common-mode voltage source model is shown in Figure 5 for an initial bridge sensor offset of -34mV (VINP - VINN). Conceptually, this divides into two 17mV offset voltages with polarities as shown. If the coarse offset adjust is set for +34mV offset (VINP - VINN), then the initial bridge offset is cancelled exactly. Any residual initial bridge offset not cancelled by the coarse offset adjust will be gained up by the front-end PGA gain and needs to be accounted for when setting the fine offset adjust by using the Zero DAC.
For this example:
VOUTMIN = 0.290908813V [(0.859475571)(2)] = 0.5000V
The output amplifier has external connections, which allow the end-user maximum flexibility in output amplifier configurations for a variety of applications. The use of the VFB and VSJ pins, are described in the Output Amplifier section.
+5V Front- End PGA Fine Gain Adjust 0.333333 < Fine Gain < 1 16- DAC Bit 51,722 counts = (0.859475571) Output Amplifier 4.5V VOUT RISO 100
2.327V + 0.290875V = 2.617875V VFRONT
Gain DAC
VS - 0.1V < VOUT < 0.1 INT/EXT FB Select Allows for Other Output Amplifier External Gain Settings Output Gain Select X2, X2.4, X3, X3.6, X4.5, X6, X9 RFO VFB R FB 100 CL > 100pF CF RLOAD
RGO
Allows for Accurate DC Feedback when Using RISO VSJ
Allows for CL Compensation External Gain Resistors, and Filtering
Figure 4. Fine Gain Adjust of the PGA309
18
PGA309
www.ti.com SBOS292 - DECEMBER 2003
The coarse offset adjust is set by Register 4 bits (4:0), with bit 4 determining the coarse offset polarity as negative for a `1' and positive for a `0'. The internal architecture of the coarse offset adjust does yield duplicate digital codes for -7(VREF/1200) and +7(VREF/1200). See the Register Description section under Register 4 for a complete mapping of the coarse offset adjust settings.
The fine offset adjust is set by the Zero DAC. RTO (referred-to-output), the Zero DAC setting is gained by the Gain DAC (fine gain adjust) and the output amplifier gain. The Zero DAC is a unipolar, 16-bit DAC, with its reference being the VREF setting of the PGA309. The range of the Zero DAC is ensured to be linear from 2%VREF to 98%VREF. The data format is 16-bit unsigned. Register 1 bits (15:0) are used for the Zero DAC setting.
+5V +5V V REF 1 .98 64k 2 .0136k 2 .48 3V 2.0136k 1.986 4k - 34mV 2 .51 7V V COS 3 4m V 10LSB s = 34mV +sig n V IN1 2.483V 1 7m V V COS /2 4-Bit + S ign DA C +sig n/- sig n Coarse Offset A djust 1LSB = (15)(V REF /12 50)
V ZERO DAC RTO = (V ZERO DAC)(F ine Gain Adjust)(Output Am plifie r Gain) +5V V REF Fine Offset Adjust 2% V REF < RA NG E < 98% V REF 1LS B = V REF /65536 Zero DAC (V ZERO DAC) = 0 .290875V (V REF = +5V , 381 3 counts)
V ZERO DAC
16-Bit DA C Zero DA C
V INP 2.5 V
4R A2 R Auto- Zero
V DIFF/2 17mV
RF V COS /2 F ront-End P GA
PGA Differentia l Am plifier A3
V ZERO DAC RTO (referred to outp ut) = 0.5V (V REF = +5V , 3813 counts)
RG RF V CM 2.5V
A uto- Ze ro
Fine Gain A djust Fine Gain A djust X0.859 4755 71
Output Am plifier Gain O utp ut A m plifier Gain X2
V OUT
V DIFF/2 17mV
V COS/2
A1 A uto- Ze ro V INN 2.5 V
R
4R
S ensor at 0p si Offset = - 34m V Comm on-Mo de = +2.5V
V IN2 2 .517V
Front-End PGA Gain = X 23.27
V COS/2 17m V
Figure 5. Coarse and Fine Offset Adjust
19
PGA309
www.ti.com SBOS292 - DECEMBER 2003
NOISE AND COARSE OFFSET ADJUST The PGA309 front-end PGA contains auto-zero operational amplifiers that allow precision, low-noise measurements free from flicker, or 1/f noise, that is typically present in regular low-voltage CMOS op amps. This auto-zero topology operates by canceling amplifier low-frequency noise and offset each clock cycle of an internal oscillator. This flattens the low-frequency noise voltage spectrum of the PGA309, leaving only a small residual clock feedthrough component at ~7kHz and its multiples. Figure 6 details the PGA309 output voltage noise spectrum for coarse offset adjust = 0mV. The advantage of this auto-zero method is that by filtering the output of the PGA309 proportionally, higher precision can be achieved, unlike conventional CMOS operational amplifiers where averaging does not improve the signal-to-noise ratio in the 1/f noise, region. In addition, the auto-zero technique allows the PGA309 input offset voltage to achieve very good temperature and time stability. The PGA309 low-frequency voltage noise density (RTI) is ~210nV/Hz. To convert this to a peak-to-peak amplitude for oscilloscope measurements, the following equation is supplied: VNPP = (eND)(BW)(crest factor) where: VNPP = voltage noise peak-to-peak (nVPP) eND = voltage noise density (nV/Hz) BW = bandwidth of interest (Hz) Crest Factor = probability factor for conversion of rms noise to peak-to-peak noise (crest factor of 6 reduces probability of seeing a larger peak-to-peak amplitude to < 0.3%). PGA309 peak-to-peak noise, RTI, BW = 10Hz:
VNPP = (210nV/Hz)(10Hz)(6) = 3984nVPP = 3.98VPP To compensate for bridge sensors with a large initial offset, the input stages of the PGA309 front-end PGA incorporate a patented circuit for the coarse offset adjust based on the auto-zero topology. For each clock cycle of the internal auto-zero oscillator, the offsets and noise of the input amplifier stages are subtracted from the input signal, and the result is summed with a small voltage produced by the Coarse Offset Adjust DAC. This resulting value becomes the input-referred offset of the PGA309. This value can be positive or negative as described in the Offset Scaling section of this data sheet. This operation does not increase the low frequency 1/f noise of the PGA309. However, the mismatches of internal elements in the Coarse Offset DAC can produce temperature and long-term stability errors on the same order as regular, traditional CMOS op amps (that is, temperature drift of input offset voltage of up to 10V/C). To produce a value that is temperature- and time-stable, the Coarse Offset DAC circuitry incorporates a chopping circuit that rotates internal components, averaging the mismatch error on the output of the Coarse Offset Adjust DAC. This produces a very timeand temperature-stable coarse offset adjust. The design compromise of the Coarse Offset DAC chopping technique is a clock feed-through glitch that can be seen at VOUT, the output of the PGA309, due to the rotating elements. With the Coarse Offset Adjust set to 0mV the clock feed-through components are practically negligible on the VOUT signal of the PGA309, as shown in Figure 7.
1
eND (V/Hz)
0.1
0.01 1 10 100 Frequency (Hz) 1k 10k 100k
Figure 6. VOUT Noise Power Spectrum for Coarse Offset Adjust = 0mV, Gain = 1152, CLK_CFG = `00' (default).
20
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Time (100s/div)
100mV/div
1mV/div
Time (100s/div)
Figure 7. VOUT Clock Feedthrough for Coarse Offset Adjust = 0mV, Gain = 1152, CLK_CFG = `00' (default). As the Coarse Offset Adjust DAC value increases the amplitude of the clock, feedthrough glitch also increases. For VREF = +5V and a full-scale Coarse Offset DAC value of 56mV, the clock feedthrough glitch is shown in Figure 8. This scope photo is for the PGA309 set in its maximum internal gain of x1152, with the Coarse Offset Adjust DAC set to -59mV and VIN set to +61mV. Referred back to the input, this VOUT glitch is only 347VPP (0.4VPP/1152). This glitch occurs at half of the internal auto-zero clock; typically, 3.5kHz. This glitch does not reflect back into the low-frequency range and can be filtered out if the signal of interest is at or below 1kHz. Figure 9 is a scope photo of VOUT peak-to-peak noise for the previous case. Figure 10 shows the VOUT noise spectrum for the case where the Coarse Offset Adjust DAC is set to -59mV and VIN = +61mV. In Figure 10, the baseband noise is about the same as when the coarse offset adjust was set to zero, as in Figure 10, but with an additional spike at about 3.5kHz.
10
Figure 8. VOUT Clock Feedthrough Glitch, Coarse Offset Adjust = 59mV, Gain = 1152, CLK_CFG = `00' (default). VOUT Glitch (RTI) = 347VPP.
1mV/div
Time (1s/div)
Figure 9. 0.1Hz to 10Hz VOUT Peak-to-Peak Noise for Coarse Offset Adjust = -59mV, Gain = 1152, VIN = +61mV.
eND (V/Hz)
1
0.1
0.01 1 10 100 Frequency (Hz) 1k 10k 50k
Figure 10. VOUT Noise Spectrum for Coarse Offset Adjust = -56mV, Gain = 1152, CLK_CFG = `00' (default).
21
PGA309
www.ti.com SBOS292 - DECEMBER 2003
For applications where the clock feedthrough glitch from the Coarse Offset Adjust DAC chopping circuitry is an issue, there are alternate modes that can be selected for the Coarse Offset DAC clocking and the auto-zero clocking of the front-end PGA. Register 5 bits (13:12) are referenced as CLK_CFG1 and CLK_CFG0, respectively. Table 2 outlines the clocking schemes available using these bits. Up to this point, CLK_CFG = `00' has been discussed.
CLK_CFG MODE 00 (default) 01 10 CLK_CFG1 BIT D13 0 0 1 CLK_CFG1 BIT D13 0 1 0 AUTO-ZERO PGA FRONT-END 7kHz typical 7kHz typical 7kHz typical, Random Clocking 7kHz typical CHOPPING COARSE OFFSET DAC 3.5kHz typical Off (none) 3.5kHz typical, Random Clocking 3.5kHz typical, Random Clocking
1mV/div
1s/div
Figure 11. 0.1Hz to 10Hz VOUT Peak-to-Peak Noise for Coarse Offset Adjust = -56mV, Gain = 1152, VIN = +57mV, CLK_CFG = `01', VNPP (RTI) = 4.44VPP. CLK_CFG = `10' mode and CLK_CFG = `11' mode turn on different clock randomization schemes for the front-end PGA auto-zero and Coarse Offset DAC chopping. Although this does not reduce the amplitude of the clock feedthrough glitch (see Figure 8), it does spread the glitch energy over a wider frequency range. This removes the fixed spike at half of the input auto-zero clock frequency, but raises the noise floor in the lower frequency range, thus increasing the baseband noise. CLK_CFG = `11' mode simply whitens the peak-to-peak noise in from the 1Hz region to about the 7kHz region by modulating both the auto-zero and chopping clocks. In CLK_CFG = `10' mode, the Coarse Offset DAC chopping clock is modulated but not the auto-zero clock. The results of these modes are shown in both voltage noise spectrum and peak-to-peak noise plots in Figure 13, Figure 14, Figure 15, and Figure 16.
11
1
1
Table 2. PGA309 Clocking Schemes In the CLK_CFG = `01' mode, the Coarse Offset Adjust DAC chopping is turned off. The clock feedthrough glitch is no longer present (see Figure 11 for 0Hz to 10Hz VOUT peak-to-peak noise) and the VOUT noise spectrum is clean (see Figure 11). However, the input Coarse Offset Adjust DAC is no longer temperaturestable. Typical span drift is generally linear with temperature and may be acceptable in applications where the PGA309 is located close to the bridge sensor and they are both calibrated together. The drift of the Coarse Offset Adjust DAC simply sums with the bridge sensor offset drift and they are both calibrated out.
10
eND (V/Hz)
1
0.1
0.01 1 10 100 1k Frequency (Hz) 10k 100k 500k
Figure 12. VOUT Noise Spectrum for Coarse Offset Adjust = -56mV, Gain = 1152, VIN = +57mV, CLK_CFG = `01'.
22
PGA309
www.ti.com SBOS292 - DECEMBER 2003
10
VOUT Noise (V/Hz)
1
5mV/div
0.1
1s/div
0.01 100
1k Frequency (Hz)
10k
100k
Figure 13. 0.1Hz to 10Hz VOUT Peak-to-Peak Noise for Coarse Offset Adjust = -56mV, Gain = 1152, VIN = +57mV, CLK_CFG = `10', VNPP (RTI) = 18.4VPP.
Figure 15. VOUT Noise Spectrum for Coarse Offset Adjust = -56mV, Gain = 1152, VIN = +57mV, CLK_CFG = `10'.
10 VOS RTI = -56mV VIN = 57mV VOUT Noise (V/Hz) 1
10mV/div
0.1
Time (100s/div)
0.01 100
1k Frequency (Hz)
10k
100k
Figure 14. 0.1Hz to 10Hz VOUT Peak-to-Peak Noise for Coarse Offset Adjust = -56mV, Gain = 1152, VIN = +57mV, CLK_CFG = `11', VNPP (RTI) = 42VPP.
Figure 16. VOUT Noise Spectrum for Coarse Offset Adjust = -56mV, Gain = 1152, VIN = +57mV, CLK_CFG = `11'.
23
PGA309
www.ti.com SBOS292 - DECEMBER 2003
REFERENCE VOLTAGE The PGA309 can be configured for use with an internal or external voltage reference. The reference voltage selected is used by the Zero DAC, Over/Under-Scale Limit, Coarse Offset Adjust DAC, Temp ADC, and Bridge Excitation Linearization Loop. Figure 17 depicts the PGA309 reference circuit. If internal reference is selected, either 2.5V or 4.096V can be chosen. In this mode, a typically better than 2% initial accuracy, low drift, 10ppm/C reference is available for internal and external use. Up to 5mA can be supplied out through the REFIN/REFOUT pin in internal mode. If external reference mode is chosen, then an external reference from +2.5V to +VSA may be applied to the REFIN/REFOUT pin. During power-on, the external reference mode is selected. Table 3 details the Register 3 bits (9:8) used for the reference mode selections.
VS Supply VS
EEPROM CONTENT AND TEMPERATURE LOOKUP TABLE CALCULATION The PGA309 has been tested to operate with EEPROM parts Microchip 24LCxx and 24AAxx. The first 16 bytes of the external EEPROM contain the programmed EEPROM flag and PGA309 configuration data for registers 3, 4, 5, and 6. The word at address 14 contains the checksum for this section, Checksum1. Table 4 details the EEPROM content.
EEPROM ADDRESS 0 2 4 6 8 10 12
CONTENT (ALL 2-BYTE VALUES) Hex 5449 = `TI': EEPROM Programmed Flag Not used, but included in the Checksum1; available for user data. Not used, but included in the Checksum1; available for user data. Value for Register 3, Reference Control and Linearization Value for Register 4: PGA Coarse Offset and Gain/Output Amplifier Gain Value for Register 5: PGA Configuration and Over/Under-Scale Limit Value for Register 6: Temp ADC Control Checksum1= 0xFFFF - SUM(Addr0 to Addr12), 16-bit wide, carryover bits are ignored Begin Lookup Table: T0; Z0; G0 Up to 16 more Lookup Table entries with slope coefficients: Ti; ZMi; GMi; optional End of Lookup Table, 3 words: hex 7FFF; 0000; Checksum2 Checksum2 = 0xFFFF - SUM(Addr16 to Current address), includes 7FFF and 0000; 16-bit words; carryover bits are ignored
External Reference
14 16 to 21
REFIN/REFOUT VREF Enable/Disable Select VREF Bandgap Reference
-- --
Table 4. EEPROM Content Table
RFB
RSET VREF Internal Set (2.5V or 4.096V) PGA309
Figure 17. PGA309 Reference Circuit
Addresses 16 and higher of the EEPROM contain the temperature coefficient Lookup Table for the Zero DAC (Fine Offset Adjust) and Gain DAC (Fine Gain Adjust). There can be up to 17 temperature index values with corresponding scale factors for the Gain DAC and Zero DAC. The values in the lookup table represent the points on the piecewise linear curves that compensate sensor span and offset drifts. The DAC values are linearly interpolated between the points. T0, T1, T2 ... Tx (where x 16) are the temperature index values in the lookup table. These are output results from the Temp ADC. The values must be monotonically increasing from minimum to maximum for the lookup table to function correctly. Note that this does not necessarily correspond to increasing temperature. For example, if a diode voltage is being measured by the Temp ADC, its readings will be
D9 RS X 0 1
D8 REN 0 1 1 VREF REFIN/REFOUT 4.096V 2.5V
REFERNCE CONFIGURATION External Reference (disable internal reference) Internal Reference Internal Reference
Table 3. Register 3 Reference Control Bits
24
PGA309
www.ti.com SBOS292 - DECEMBER 2003
decreasing with temperature. However, the Lookup Table must still be built from minimum Temp ADC reading to the maximum. The data format for Tx is 16-bit data with a format dependent upon which Temp ADC mode is selected (see Register 6, Temperature ADC Control Register, for a detailed register description). Z0 is the value of the Zero DAC setting for temperatures T0 and below. Z0 data format is unsigned 16-bit data. The equation for the Zero DAC value is: Zi + VZdesired @ 65, 536 VREF
The end of the Lookup Table is flagged by temperature index value TEND = 0x7FFF in the temperature index data. The ZME value of this entry is ignored but is included in the checksum. The ZME value should be set to zero. The GME value of this entry becomes Checksum2, the checksum for the second part of the EEPROM. Table 5 shows an example Lookup Table and details the calculation of its values. Figure 18 illustrates the concept of the Gain DAC temperature coefficients stored in the EEPROM according to Table 5. G0-G7 are exact desired settings at T0-T7, respectively, for the Gain DAC. GM1-GM7 are the slopes of the piecewise linear curves that connect G0-G1, G1-G2, G2-G3, G3-G4, G4-G5, G5-G6, and G6-G7. For this example, we wish to see how the lookup logic with interpolation algorithm of the PGA309 will accurately calculate the setting for the Gain DAC at TREAD = 25C, which does not fall on an exact data point (Tx, Gx).
G0 1.0
GM1
G0 is the value of the Gain DAC setting for temperatures T0 and below. G0 data format is unsigned 16-bit data. The equation for the Gain DAC value is: G i + Gaindesired * 1 @ 3 @ 65, 536 3 2 ZM1, ZM2 ... ZMx are multiplying slope factors for each piecewise linear segment for the Zero Adjustment DAC. They are calculated based on the desired values Z1, Z2 ... Zx (calculated same as Z0) of the Zero DAC for T1, T2 ... Tx respectively. The equation for calculating the ZMi slope factors is: (Z * Z i*1) ZM i + 256 i (T i * T i*1) The ZMx scale factor of 256 is to format the decimal value for PGA309 internal binary arithmetic. These numbers are 16-bit, Two's Complement data format. See Table 5 for an example of the lookup table. GM1, GM2 ... GMx are multiplying slope factors for each piecewise linear segment for the Gain Adjustment DAC. The equation for calculating the GMi slope factors is: GM i + 256 (G i * G i*1) (T i * T i*1)
G1
Gain DAC Value (decimal)
0.8
GM2
G2 G5 G7
GM6 GM7
0.6
GM3 G3 GM4 GM5
0.4
G4
G6
0.2
0 -40 T0
-30 T1
-20 T2
-10 T3
0 T4
10 T5
20 T6
30 T7 TREAD
Temperature (_C)
Figure 18. Gain DAC Temperature Coefficients-- Definition Example
DESIRED VALUES IN LOOKUP TABLE POINT# 0 1 2 3 4 5 6 7 End TEMP (C) -40 -30 -20 -10 0 10 20 30 ... VZERO (V) 0.1 0.2 1 1 2 1.5 1 2 ... GFINE (V/V) 1 0.9 0.7 0.4 0.33333 0.6 0.4756 0.6543 ...
LOOKUP TABLE (DECIMAL) ADC OUT -640 -480 -320 -160 0 160 320 480 32767 ZERO COEF 1311 2096 16778 0 20971 -10485 -10486 20971 0 GAIN COEF 65535 -15726 -31458 -47186 -10486 41942 -19566 28107 Checksum
LOOKUP TABLE (HEX) TEMP FD80 FE20 FEC0 FF60 0000 00A0 0140 01E0 7FFF ZM 051F 0830 418A 0000 51EB D70B D70A 51EB 0 GM FFFF C292 851E 47AE D70A A3D6 B392 6DCB B622
Table 5. Lookup Table Example: VREF = 5V, Internal Temperature Sensing Mode
25
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Table 6 outlines the algorithm used inside the PGA309 for linear interpolation and calculation of the Gain DAC setting for TREAD = 25C. Table 5 shows example calculations for GM1-GM7 at T1-T7 given values for G1-G7. The starting values (T0 and G0) are also defined. From the plot in Figure 18, it is shown that at the currently read temperature (TREAD = 25C), there should be a mathematical value of 0.56495 for the Gain DAC setting if the PGA309 lookup logic with interpolation algorithm is working correctly. Each time the Temp ADC does a conversion, it reads the entire external EEPROM. The first half, as described previously, is dedicated to fixed setup parameters for the PGA309 that do not change with temperature. As the PGA309 reads the second half of the EEPROM, it begins a running calculation of the Gain DAC setting with temperature (the PGA309 runs a similar calculation for the Zero DAC setting). This model includes an accumulator named GAC (G Accumulator). When the PGA309 reads T0, the initial Gain DAC setting (G0) is stored in GAC0 (GAC at T0 read). Next, T1 is read and slope GM1 is multiplied by the difference between T1 and T0 and added to GAC0 to form the new accumulator value, GAC1 (GAC at T1 read). This process continues in a sequential fashion as the PGA309 reads through the entire Lookup Table. As each temperature index value (Tx) is read, it is compared against ADCREAD, the current Temp ADC conversion result. If Tx > TREAD, it is known that TREAD is between Tx and T(x-1). In this example, it occurs as T7 is read. The accumulator contents, GAC6 (GAC at T6), are modified by the addition of (TREAD - T6)(GM7). The resulting GAC_ADCREAD is the linearly
interpolated setting for the Gain DAC at TREAD = 25C. The rest of the EEPROM is still read for error checking with Checksum2 at the end of the Lookup Table. The Zero DAC ZMx multiplying scale factors for temperature correction are computed the same as those discussed for the Gain DAC. The internal PGA309 lookup logic with interpolation algorithm calculates the Zero DAC setting for TREAD in the same manner as outlined for the Gain DAC. Please note that the values of the Gain DAC and Zero DAC must always be in their respective ranges to produce correct results: 2%VREF ZeroDAC 98% VREF 0.33333 (V/V) GainDAC 1 (V/V) FAULT MONITOR Monitoring of fault condition sensors is provided on the PGA309 through nine internal comparators. Refer to Figure 19. These comparators are grouped into two sets: Internal Fault Comparators and External Fault Comparators. In Figure 19, these are denoted as EXT for those in the External Fault Comparator group and by INT for those in the Internal Fault Comparator group. The external fault comparators are used to monitor proper operation of the bridge sensor and report input fault conditions. Table 7 enumerates the possible fault cases for a bridge sensor and the associated fault comparator outputs for each fault condition. Due to the extremely low input bias currents of the PGA309, if fault detection of floating inputs (sensor disconnected entirely from one or both of the PGA309 inputs) is to be accurately reported,
CALCULATION ALGORITHM FOR GAIN VALUE AT T = 25C (TEMP ADC = 0X0190 400 DECIMAL) POINT# 0 1 2 3 4 5 6 7 end TEMP INDEX (DECIMAL) -639 -479 -319 -159 0 160 320 480 32767 GAIN INDEX (DECIMAL) 65535 -15725 -31457 18350 -10485 -23593 -19565 28107 GAC CALCULATION GAC0 = G0 GAC1 = GAC0 + GM1(T1 - T0) GAC2 = GAC1 + GM2(T2 - T1) GAC3 = GAC2 + GM3(T3 - T2) GAC4 = GAC3 + GM4(T4 - T3) GAC5 = GAC4 + GM5(T5 - T4) GAC6 = GAC5 + GM6(T6 - T5) T7 > ADCREAD " YES! GACTREAD = GAC6 + GM7(ADCREAD - T6) RUNNING GAC VALUE (DECIMAL) 65535 55707 36046 47515 41003 26257 14029 22812 ACTUAL DAC GAIN (V/V) 0.99999 0.90001 0.70001 0.81668 0.75044 0.60043 0.47604 0.56539
The Lookup Table is read to the end to verify Checksum2
NOTE: GAC = G Accumulator: running total that is computed starting with G0, at T0, every time the Temp ADC converts a new value, which causes a new calculation update cycle to occur by reading the EEPROM from beginning to end.
Table 6. Gain DAC Temperature Coefficients--Calculation Example
26
PGA309
www.ti.com SBOS292 - DECEMBER 2003
it is necessary to add either pull-up or pull-down resistors to each of these inputs (VIN1 and VIN2), shown in Figure 19 as optional. The value of these resistors can be between 1M and 10M in order to minimize signal loading of the bridge sensor's output. Offset and other errors from these optional resistors will be cancelled out
during the PGA309 + sensor calibration. Table 8 itemizes the special cases for floating inputs on the PGA309 when using pull-up resistors. Table 9 lists the special cases for floating inputs on the PGA309 when using pull-down resistors. All other fault cases not listed as special cases are the same as those detailed in Table 7.
VEXC
VEXC Circuit A2SAT_LO (ALM5)
Min Ref Select VSA - 1.2V (VEXC - 100mV)(1) EXT INP_HI (ALM1) 100mV
INT
VSA - 120mV INT EXT 100mV Fine Offset DAC MUX CN TL VINP R VIN2 A2 RF R B2 Bridge Sensor R B3 RB4 R VIN1 VIN N A1 4R RB1 RG RF A3 V IA_OUT 4R INP_LO (ALM0)
A2SAT_HI (ALM6)
Optional Pull- Down Resistor 1M to 10M
VSA - 1.2V INT
A3_VCM (ALM4)
Fine Gain Adjust DAC
VOU T
RFO
RG O INT EXT Optional Pull- Down Resistor 1M to 10M 100mV Min Ref Select VSA - 1.2V (VEXC - 100mV)(1) EXT VSA - 120mV INN_HI (ALM3) INT INN_LO (ALM2) 100mV A1SAT_LO (ALM7)
A1SAT_HI (ALM8)
NOTE: (1) When VEXC is enabled, a minimum reference selector circuit becomes the reference for the INN_HI and INP_HI comparator threshold. This minimum reference selector circuit uses VEXC - 100mV and VSA - 1.2V and compares the VINX pin to the lower of the two references. This ensures end PGA amplifier relative to VSA. accurate fault monitoring in conditions where VEXC might be higher or lower than the input voltage range of the front-
Figure 19. PGA309 Fault Monitor Circuitry
27
PGA309
www.ti.com SBOS292 - DECEMBER 2003 LOGIC LEVEL OUTPUTS CASE Normal RB1 Open RB2 Open RB3 Open RB4 Open RB1 Short RB2 Short RB3 Short RB4 Short Open Sensor GND Open Sensor VEXC VEXC Short GND VIN1 (VINP) Open(2) VIN2 (VINN) Open(2) VIN1 (VINP) Short GND VIN2 (VINN) Short GND VIN1 (VINP) Short VEXC VIN2 (VINN) Short VEXC VIN1 (VINP), VIN2 (VINN) Open(2) VIN2 (VINN) (V) 1.7 1.7 0 3.4 1.7 1.7 3.4 0 1.7 3.4 0 0 1.7 ~VSA-0.7 1.7 0 1.7 3.4 ~VSA-0.7 VIN1 (VINP) (V) 1.7 0 1.7 1.7 3.4 3.4 1.7 1.7 0 3.4 0 0 ~VSA-0.7 1.7 0 1.7 3.4 1.7 ~VSA-0.7 VIA_OUT (V) Linear ~0 ~VSA ~0 ~VSA ~VSA ~0 ? ~0 ~0 ~0 ~0 ~VSA ~0 ~0 ~VSA ~VSA ~0 Linear? INN_HI (ALM3) 0 0 0 1 0 0 1 0 0 1 0 1(1) 0 0 0 0 0 1 0 INN_LO (ALM2) 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 INP_HI (ALM1) 0 0 0 0 1 1 0 0 0 1 0 1(1) 0 0 0 0 1 0 0 INP_LO (ALM0) 0 1 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 Typically drifts to over-scale limit slowly; no Ext Faultdetect (ALM7), Int Fault set = A1 Sat Low Under-scale limit on VOUT, no fault detect--Int or Ext Over-scale limit on VOUT, no fault detect--Int or Ext COMMENTS
VIN1 (VINP), VIN2 (VINN) Short GND VIN1 (VINP), VIN2 (VINN) Short VEXC
0 3.4
0 3.4
~VSA ~0
0 1
1 0
0 1
1 0
NOTE: VSA = +5V, VREF = +4.096V, KEXC = 0.83, KLIN = 0, and VEXC = 3.4V. (1) Typically, a logic 1, but not guaranteed by design and nature of fault. (2) Accurate detection of these faults requires a pull-up or pull-down resistor on each input (VIN1 and VIN2).
Table 7. Bridge Sensor Faults and Fault Comparator States--VIN1 and VIN2: no pull-up or pull-down resistors
LOGIC LEVEL OUTPUTS SPECIAL CASE(1) VIN1 (VINP) Open VIN2 (VINN) Open VIN1 (VINP), VIN2 (VINN) Open VIN2 (VINN) (V) 1.7 VEXC VEXC VIN1 (VINP) (V) VEXC 1.7 VEXC VIA_OUT (V) ~VSA ~0 ~0 INN_HI (ALM3) 0 1 1 INN_LO (ALM2) 0 0 0 INP_HI (ALM1) 1 0 1 INP_LO (ALM0) 0 0 0
NOTE: VSA = +5V, VREF = +4.096V, KEXC = 0.83, KLIN = 0, and VEXC = 3.4V. (1) All other cases not listed are the same as those for Table 7.
Table 8. Bridge Sensor Faults and Fault Comparator States--VIN1 and VIN2: 10M pull-up resistors to VEXC
LOGIC LEVEL OUTPUTS SPECIAL CASE(1) VIN1 (VINP) Open VIN2 (VINN) Open VIN1 (VINP), VIN2 (VINN) Open VIN2 (VINN) (V) 1.7 ~0 ~0 VIN1 (VINP) (V) ~0 1.7 ~0 VIA_OUT (V) ~VSA ~0 ~0 INN_HI (ALM3) 0 0 0 INN_LO (ALM2) 0 1 1 INP_HI (ALM1) 0 0 0 INP_LO (ALM0) 1 0 1
NOTE: VSA = +5V, VREF = +4.096V, KEXC = 0.83, KLIN = 0, and VEXC = 3.4V. (1) All other cases not listed are the same as those for Table 7.
Table 9. Bridge Sensor Faults and Fault Comparator States--VIN1 and VIN2: 10M pull-down resistors to GND
28
PGA309
www.ti.com SBOS292 - DECEMBER 2003
When VEXC is enabled, external fault comparators INP_HI and INP_LO have a minimum reference selector circuit that selects between a typical trip point of either VEXC - 100mV or VSA - 1.2V. This ensures accurate fault monitoring in conditions where the linearization circuitry increases VEXC, and the bridge sensor has fault conditions that violate the input voltage range, relative to VSA, of the front-end PGA in the PGA309. If VEXC is disabled, these comparators default to the VSA - 1.2V threshold. The internal fault comparators are used to monitor the front-end PGA internal nodes of the PGA309 (see Figure 19). When PGA309 + Sensor calibration is in process, it is crucial to have the internal comparator group enabled because it can alert the user to an internal node violation. Such a violation may still yield a voltage within the expected linear output range, but it will not be an accurate one. Each of the front-end amplifiers, A1 and A2, of the front-end PGA have their outputs monitored for both saturation to the positive supply or to ground. If either of these comparators trips during calibration, it is an indication of an out-of-range scaling condition either due to the incorrect front-end PGA gain select or coarse offset adjust. The A3
amplifier in the front-end PGA is also monitored for common-mode violations as can occur if the Zero DAC is combined incorrectly with the front-end PGA gain select. Each individual internal and external fault comparator can be read through one of the digital interfaces: Two-Wire or One-Wire. The current results are stored in Register 8--Alarm Status Register. When the PGA309 output is enabled, the value of the Alarm Status Register reflects the current state of the fault comparators. When VOUT is disabled, the value in the register is the comparator status immediately before the output was disabled. This allows for easier identification and debugging of the Three-Wire mode (PRG shorted to VOUT). See the One-Wire Operation with PRG Shorted to VOUT section for details. In addition, each group of comparators, internal fault and external fault, can be programmed such that if any comparator in their respective group is logic high, indicating a fault, the PGA309 output (VOUT) will be forced to a fault indicating voltage level of either positive (VSA - 0.1V max with a 10k load) or negative (0.1V max with a 10k load). The logic for this is shown in Figure 20.
External Comparator Fault Flag INP_HI INP_LO External INN_HI Comparators INN_LO ALM2 ALM3 ALM0 ALM1 ALM8 ALM7 ALM4 ALM6 ALM5 A2SAT_LO A2SAT_HI Internal A3_VCM Comparators A1SAT_LO A1SAT_HI 1 = fault INTEN 1 = enable 0 = disable Alarm Status Register 1 = fault EXTEN 1 = enable 0 = disable
EXTPOL 1 = Force VOUT High 0 = Force VOUT Low 1 = Close 0 = Open VSA '0' '1'
Output Amp
VOUT
1 = Close 0 = Open
Internal Comparator Fault Flag
INTPOL 1 = Force VOUT High 0 = Force VOUT Low
VSA '0' '1'
Figure 20. Fault Monitor Comparator Logic
29
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Configuration for the fault monitor comparator logic is provided in Register 5--PGA Configuration and Over/Under Scale Limit. The individual comparator outputs in each group are combined to generate an Internal Comparator Fault flag and an External Comparator Fault flag. For the External Comparator group (EXTEN), Register 5 (bit 11) enables or disables whether the External Comparator Fault flag will be sent forward to force VOUT to a fault indication state. For the Internal Comparator group (INTEN), Register 5 (bit 10), enables or disables whether the Internal Comparator Fault flag will be sent forward to force VOUT to a fault indication state. For each of the comparator groups, there is programmability of the fault indication state on VOUT (either VSA or GND). INTPOL, Register 5 (bit 8), selects this state for the Internal Comparator group and EXTPOL, Register 5 (bit 9) selects for the External Comparator group. The External Comparator Fault flag has priority over the Internal Comparator Fault flag, as shown in Figure 20. For example, if the Internal Fault Comparator group is set to force VOUT low and the External Fault Comparator group is set to force VOUT high, and both groups detect a fault (which is possible if both are enabled), then the External Fault Comparator group prevails and VOUT is forced high. This is to ensure that for most real-world applications, a critical sensor fault would be reported as priority over an internal node violation. Assuming there is a valid linear output on VOUT at the time of a detected fault, the fault logic always prevails (if enabled), and will override the linear output to indicate a fault on VOUT as positive or negative VOUT saturation. OVER/UNDER SCALE The Over-Scale and Under-Scale Limit circuit provides a programmable upper and lower clip limit for the PGA309 output voltage. This circuit can be enabled by setting Register 5, bit D6 to D1. When combined with the Fault Monitor circuitry, system diagnostics can be performed to determine if a conditioned sensor is defective or if the process being monitored by the sensor is out of range. Figure 21 details the key sections of the Over-Scale and Under-Scale Limit circuit. The selected PGA309 VREF is divided down by a precision resistor string to form the over-scale and under-scale thresholds, as shown in Table 10 and Table 11. Register 5 bits [5:0] set the desired thresholds. These resistor ratios are extremely accurate and produce no significant initial or temperature errors. As shown in Figure 21, there are two separate comparators: over-scale and under-scale, which use the over-scale or under-scale threshold, respectively, and determine where the PGA309 output (VOUT) will be clipped. The dominant errors in the Over-Scale and Under-Scale Limit circuit are in the comparator offsets and offset temperature drifts.
30
VR E F X1 On = '1' Over-Scale Threshold (Select 1- 7) of- Output Amplifier Output Stage Over-Scale Comparator
V FB
Over-Scale Limit
Output Amp
VO U T
R GO (Select 1- 8) of- Under-Scale Threshold
R FO
Under-Scale Limit
On = '1' Under-Scale Comparator X1
Figure 21. Over-Scale and Under-Scale Limit Circuit
OVER-SCALE THRESHOLD (V) 4.854 4.805 4.698 4.580 4.551 3.662 2.764 Reserved
HL2 [5] 0 0 0 0 1 1 1 1
HL1 [4] 0 0 1 1 0 0 1 1
HL0 [3] 0 1 0 1 0 1 0 1
OVER-SCALE THRESHOLD 0.9708 VREF 0.9610 VREF 0.9394 VREF 0.9160 VREF 0.9102 VREF 0.7324 VREF 0.5528 VREF --
Table 10. Under-Scale Threshold Selections (Register 5 Bits [5:0]). VREF = +5V.
UNDER-SCALE THRESHOLD (V) 0.127 0.147 0.176 0.196 0.225 0.254 0.274 0.303
LL2 [2] 0 0 0 0 1 1 1 1
LL1 [1] 0 0 1 1 0 0 1 1
LL0 [0] 0 1 0 1 0 1 0 1
UNDER-SCALE THRESHOLD 0.02540 VREF 0.02930 VREF 0.03516 VREF 0.03906 VREF 0.04492 VREF 0.05078 VREF 0.05468 VREF 0.06054 VREF
Table 11. Over-Scale Threshold Selections (Register 5 Bits [5:0]). VREF = +5V. The design considerations in using the Over-Scale and Under-Scale Limit circuit are best understood through a definition by example.
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Example: Over/Under-Scale Calculation
Given: Absolute Scale System--PGA309 connected to a system ADC (see Figure 22) System ADC Reference: VREF ADC = 4.096V PGA309 Reference: VREF = 4.096V (use internal reference) Operating Temperature Range: -40C to +125C PGA309 VSA, VSD = +5V External Fault Monitor; Trip High when Fault Detected Recommended levels to allow for Over-Scale and Under-Scale Limits as well as Fault Detection. A) Over-Scale Limit B) Under-Scale Limit C) Useable Linear PGA309 Output Range D) System ADC Trip Points: Over-Scale Under-Scale Fault Detect
Find:
3. Calculate the over-scale and under-scale min and max trip points over the operating temperature range for each 1. Analyze the worst case offset errors on the over-scale and over-scale and under-scale threshold (refer to Table 13). under-scale comparators over the operating temperature range. Table 12 contains key electrical characteristics Over-Scale Min and Max Trip Points: OS min = VREF min (OS ratio) - VOS min needed for this computation. OS max = VREF max (OS ratio) + VOS max Over-Scale Comparator Offset Calculation: Under-Scale Min and Max Trip Points: Over-Scale Temperature Drift: US min = VREF min (US ratio) - VUS min -40C to 25C: -24.05mV = (+0.37mV/C)(-40C - 25C) US max = VREF max (US ratio) + VUS max 25C to +125C: +37.00mV = (+0.37mV/C)(+125C - 25C) Over-Scale Offset Min and Max: VOS min = +6mV -24.05mV = -18.05mV VOS max = +114mV + 37.00mV = +151.00mV Under-Scale Comparator Offset Calculation: 4. From the over-scale and under-scale min and max trip point calculations, choose the best selection that will allow for the optimum system ADC range budget (see Figure 23). For this example, the PGA309 is scalable for a linear output of 8% to 92% of the system ADC reference. In addition, we can set reasonable trip points for detecting over-scale limit, under-scale limit, and fault detect.
Solution:
Under-Scale Temperature Drift: -40C to 25C: +9.75mV = (-0.15mV/C)(-40C - 25C) 25C to +125C: -15.00mV = (-0.15mV/C)(+125C - 25C) 5. Check that the PGA309 VOUT can support the voltage swings defined in the SystemADC range budget. Table 14 Under-Scale Offset Min and Max: confirms that for our example the PGA309 VOUT can meet VUS min = -7mV + 9.75mV = -2.75mV the limiting conditions for our desired scaling. VUS max = -93mV -15.00mV = -108mV 2. Analyze the worst-case change in VREF over the operating temperature range. VREF Temperature Drift: -40C to +125C: [(+10ppm/C)/(1e6)](+125C- -40C)VREF = +0.00165 VREF VREF Min and Max: VREF min = 4.00V - (0.00165)(4.00V) = 3.9934V VREF max = 4.14V + (0.00165)(4.00V) = 4.1466
31
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Since the PGA309 + sensor is usually calibrated together as a system, the over-scale and under-scale limits can be measured per device at the operating temperature extremes, and the final limits adjusted as desired for optimum scaling. In
a ratiometric scaled system, the reference error will not need to be included in the over-scale and under-scale trip point calculations.
+5V +5V VSD SDA Two- Wire EEPROM PRG SCL VOUT VEXC RISO(1) 100 CL(2) 10nF VSA REFIN/REFOUT Sensor Out GND
+5V
+5V
VREF ADC (4.096V)
+5V
ADC
10101
System ADC
PGA309
VIN2
VFB
RFB(1) 100
CF(3) 150pF
Bridge Sensor
VIN1
VSJ
TEMPIN
Test
GNDA
GND D
NOTES: (although not needed in all applications) (1) R ISO and RFB provide the PGA309 with overvoltage protection on Sensor Out. (2) C L provides EMI/RFI filtering. (3) C F provides the PGA309 with stability for capacitive load of CL.
Figure 22. Absolute Scale System--PGA309 Connected to a System ADC
PARAMETER Over-Scale Comparator Offset Over-Scale Comparator Offset Drift Under-Scale Comparator Offset Under-Scale Comparator Offset Drift VREF2 VREF2 Drift 4.00 -7 MIN +6 TYP +60 +0.37 -50 -0.15 4.096 +10 4.14 -93 MAX +114 UNITS mV mV/C mV mV/C V ppm/C
Table 12. Electrical Characteristics for Over-Scale and Under-Scale Comparators and VREF
32
PGA309
www.ti.com SBOS292 - DECEMBER 2003 THRESHOLD U = UNDER-SCALE O = OVER-SCALE U7 U6 U5 U4 U3 U2 U1 U0 O6 O5 O4 O3 O2 O2 O0
THRESHOLD RATIO TO VREF 0.0605 0.0547 0.0508 0.0449 0.0391 0.0352 0.0293 0.0254 0.5528 0.7324 0.9102 0.9160 0.9394 0.9610 0.9708
MIN TRIP (V) 0.1300 0.1066 0.0910 0.0676 0.0442 0.0287 0.0053 -0.0103 2.2164 2.9336 3.6436 3.6668 3.7602 3.8465 3.8856
MIN TRIP (%VREF ADC) 3.1741 2.6028 2.2225 1.6512 1.0799 0.6997 0.1283 -0.2519 54.1101 71.6203 88.9549 89.5204 91.8018 93.9077 94.8631
MAX TRIP (V) 0.2500 0.2257 0.2096 0.1853 0.1610 0.1448 0.1205 0.1043 2.1320 2.8767 3.6140 3.6380 3.7351 3.8246 3.8653
MAX TRIP (%VREF ADC) 6.1044 5.5111 5.1163 4.5231 3.9298 3.5350 2.9418 2.5470 52.0505 70.2324 88.2321 88.8192 91.1881 93.3748 94.3669
TYP TRIP (V) 0.1900 0.1662 0.1503 0.1264 0.1026 0.0867 0.0629 0.0470 2.1742 2.9051 3.6288 3.6524 3.7476 3.8355 3.8754
TYP TRIP (%VREF ADC) 4.6392 4.0569 3.6694 3.0871 2.5049 2.1173 1.5351 1.1475 53.0803 70.9263 88.5935 89.1698 91.4949 93.6412 94.6150
Table 13. Over-Scale and Under-Scale Min and Max Trip Point Calculations
100% of VREF ADC ADC Upper Headroom 98% of VREF ADC 96% V REF ADC-Fault Flag Trip Point 94.9% VREF ADC-Over-Scale Limit (max) 94.6% V REF ADC-Over-Scale Limit (typ) 94.3% V REF ADC-Over-Scale Limit (min) 93% VREF ADC-Over-Scale Trip Point 92% of VREF ADC Real-World Useable ADC Range PGA309 Linear Output Range
8% of VREF ADC 7% V REF ADC-Under-Scale Trip Point 6.1% VREF ADC-Under-Scale Limit (max) 4.6% VREF ADC-Under-Scale Limit (typ) 3.1% V REF ADC-Under-Scale Limit (min) 2% of VREF ADC 0% of VREF ADC
ADC Lower Headroom
Figure 23. System ADC Range Budget for Over-Scale, Under-Scale, and Linear Output
PGA309 VOUT (V) 3.93216 0.126976 PGA309 VOUT LIMIT (V) 4.9 0.1
LIMITING CONDITION 96% VREF ADC--Fault Flag Trip Point 3.1% VREF ADC--Under-Scale Limit (min)
NOTE: VREF ADC = 4.096V, VSA = 5V
Table 14. PGA309 VOUT Limits for System ADC Range Budget
33
PGA309
www.ti.com SBOS292 - DECEMBER 2003
LINEARIZATION FUNCTION Many bridge sensors have an inherent nonlinearity of their output with applied pressure. Figure 24 illustrates a typical nonlinearity correction using the PGA309 linearization circuitry.
2.7 2.4 2.1 Nonlinearity (%FSR) 1.8 1.5 1.2 0.9 0.6 0.3 0 -0.3 0 1 2 3 4 5 6 7 8 9 10 Bridge Output (mV) Corrected Bridge Output Uncorrected Bridge Output
and sums it together with a portion of the output voltage (VOUT) to compensate for the bow-shaped nonlinearity of the bridge sensor output versus pressure. Using this technique, it is possible to compensate for parabolic nonlinearity resulting in up to to a 20:1 improvement over an uncompensated bridge output. If no linearity correction is desired, the sensor should be connected directly to the reference voltage (absolute system) or supply (ratiometric system). In applications not using linearization, both the VEXC buffer and linearization DAC may be disabled by setting the appropriate Register 3 bits (10, 7:0) to `0'. This results in 50A to 100A of lower total quiescent current. In systems where fault monitoring is critical, it is better to use VEXC and KLIN = 0. This optimizes fault monitoring comparator operation. The output signal-dependence (VOUT dependence) of the bridge excitation (VEXC) adds a second-order term to the overall system transfer function (PGA309 + bridge sensor). The LinDAC (see Figure 26) scales a portion of VOUT that is then summed with a scaled version of the reference voltage, VREF. The LinDAC code can be set to compensate for each individual bridge sensor nonlinearity. As illustrated in Figure 26, there are two ranges available in the PGA309 linearization loop to accommodate a variety of sensor nonlinearities and VREF combinations.
Figure 24. Bridge Pressure Nonlinearity Correction The PGA309 contains a dedicated circuit for sensor voltage excitation and linearization, as shown in Figure 25. The linearization loop scales the selected VREF
KLIN VEXC
KEXC Front End PGA + Fine Gain Adjust + Output Amplifier
PGA309 Bridge Excitation Linearization Loop
VREF
Fine Offset DAC VFB
P
FSS(1) and PNL(2) Pressure Sensor
+Sensor Out -Sensor Out
VIN1 VIN2 XG
VOUT
NOTES: (1) FSS = Full- Scale Sensitivity of sensor. (2) PNL = Pressure NonLinearity of sensor.
Figure 25. Bridge Excitation Linearization Loop
34
PGA309
www.ti.com SBOS292 - DECEMBER 2003
X0.166
(-0.166VFB < VLIN_DAC < +0.166VFB)
7- + Sign Bit DAC
KLIN
Range 0
KEXC
X0.83
LinDAC (Linearization DAC)
REFIN/REFOUT
4.096V Internal Select
2.5V
VEXC Output Amplifier
VFB VOUT
X0.124
(-0.124VFB < VLIN_DAC < +0.124VFB)
7- + Sign Bit DAC
KLIN
Range 1
KEXC
X0.52
LinDAC (Linearization DAC)
REFIN/REFOUT
4.096V Internal Select
2.5V
Figure 26. Linearization Circuitry To determine the value for the LinDAC, also called the linearization coefficient KLIN, the nonlinearity of the bridge sensor with constant excitation voltage must be known. The PGA309 linearization circuitry can only compensate for the parabolic-shaped portions of a sensor's nonlinearity with applied pressure. This nonlinearity is assumed to be constant over temperature or the temperature variations are assumed to be an insignificant contribution to the system error budget. For the typical PGA309 application, the KLIN factor is not adjusted with temperature changes. Optimum correction occurs when maximum deviation from a linear output occurs at mid-scale (see Figure 27 and Figure 28). Sensors with nonlinearity curves similar to that of Figure 27, but not peaking at exactly mid-scale, can still be substantially improved. A sensor with an S-shaped nonlinearity curve (equal positive and negative nonlinearity) cannot be improved by using the PGA309 Linearization Circuitry.
35
PGA309
www.ti.com SBOS292 - DECEMBER 2003
10 9 8 Bridge Output (mV) 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Normalized Stimulus (PIN/PMAX) Negative Nonlinearity BV = -0.025 (-2.5% FSR) Positive Nonlinearity BV = +0.025 (+2.5% FSR)
System Definitions PMIN--Minimum System Input Pressure PMAX--Maximum System Input Pressure FSS--Full Scale Sensitivity at PMAX (that is, 5mV/V) BV--Bridge Nonlinearity with Applied Pressure. Maximum error at mid-scale input range (mid-pressure scale maximum error %FS: +2.5%FS = 0.025, -2.5% = -0.025) P--Pressure Input PNL--Nonlinear Pressure Output of Bridge with Linear Pressure Input P VOUT MIN--Minimum PGA309 VOUT Voltage for PMIN Bridge Input VOUTMAX--Maximum PGA309 VOUT Voltage for PMAX Bridge Input VREF--PGA309 Reference Voltage KLIN--PGA309 Linearization Coefficient KEXC--PGA Excitation Coefficient. Scale factor on VREF.
Positive Nonlinearity BV = +0.025 (+2.5% FSR)
Figure 27. Parabolic Bridge Output vs Pressure
3.0 2.4 1.8 Nonlinearity (% FSR) 1.2 0.6 0 -0.6 -1.2 -1.8 -2.4 -3.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Normalized Stimulus (PIN/PMAX) Negative Nonlinearity BV = -0.025 (-2.5% FSR)
KP--Pressure Constant. Converts linear input pressure to nonlinear pressure detected by sensor. Referenced to full-scale input pressure. G--Total PGA309 Gain of VOUT/VIN. G = Front-End PGA Gain + Fine Gain Adjust + Output Amplifier Gain. VEXC--Bridge Voltage Excitation (generated by PGA309 based on VREF, KLIN, KEXC, VOUT) Key Linearization Design Equations Equation 1--Nonlinear pressure conversion for parabolic bridge sensor nonlinearity (BV = positive for a positive parabolic nonlinearity, Bv = negative for a negative parabolic nonlinearity; see Figure 28):
2
Figure 28. Parabolic Bridge Nonlinearity vs Pressure Either positive or negative bridge nonlinearities can be compensated by the proper setting of the LinDAC polarity. To correct for positive bridge nonlinearity (upward bowing--see Figure 28), the LinDAC value should be set positive. For negative bridge nonlinearity (downward bowing--see Figure 28), set the LinDAC value negative. The excitation voltage (VEXC) directly scales the bridge sensor output and therefore affects the gain and offset when the linearization loop is used. Key definitions and design equations for linearization circuit are given in the next section. the
PNL :+ P ) 4(B V) @ P MAX @
P P MAX
*
P P MAX
(1)
Equation 2--Pressure constant. PNL referenced to full scale input pressure:
2
P ) 4(B V) @ P MAX @ K P :+
P P MAX
*
P P MAX
P MAX
(2)
36
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Equation 3--Linearization Constant:
K LIN :+
VOUT
Key Ideal Design Equations Equation 8--Ideal Gain, G
) VOUT
4 @ B V @ V REF @ K EXC
MAX
* VOUT
MIN
*2@B
V
@
VOUT
MAX
MIN
(3)
G IDEAL :+
VOUT MAX * VOUT MIN V REF @ FSS
(8)
Equation 4--Total PGA309 Gain: Equation 9--VOUT Ideal.
G :+ VOUT MAX * VOUT MIN V REF @ K EXC @ FSS ) K LIN @ VOUT MAX @ FSS
(4)
VOUT IDEAL(P) :+ FSS @ GIDEAL @
P @ V REF ) V OS P MAX
(9)
Equation 5 --PGA309 VOUT:
VOUT :+ FSS @ G @ K P @ V REF @ K EXC ) VOUT MIN 1 * FSS @ G @ KP @ KLIN
Equation 10--Full-Scale Range of Output (5) FSR :+ VOUT MAX * VOUT MIN Equation 11--VOUT Error (%FSR). (6) VOUT ERR_FSR :+ VOUT * VOUT IDEAL @ 100 FSR (10)
Equation 6 --PGA309 VEXC: V EXC :+ VREF @ KEXC ) KLIN @ V OUT Equation 7--LinDAC Counts Conversion: Decimal#Counts + |Desired KLIN| Full-Scale Ratio 128
(11)
(7)
Example: Linearization DAC Counts Conversion
Given: Find: Solution:
(Range 1: -0.166VFB < LinDAC < +0.166VFB) Lin DAC value for KLIN = -0.082
1. Decimal # Counts = 0.082 / (0.166 / 128) = 63.228 2. Use 63 counts 0x3F 0011 1111 3. However, -0.082 is needed. Add 1 in the sign bit (MSB, Bit 7) for negative ratio: 4. Final LinDAC setting: 1011 1111 0xBF
37
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Example: Linearization Design
SYSTEM INPUTS PMIN PMAX FSS Bv VOUTMAX VOUTMIN VREF KEXC PGA309 CALCS KLIN G VOUTIDEAL GIDEAL FSR P (psi) 0 10 20 30 40 50 60 70 80 90 100 VOUT (V) 0.5000 0.8986 1.2981 1.6983 2.0990 2.5000 2.9010 3.3017 3.7020 4.1015 4.5000 160 4 VEXC (V) 4.2053 4.2494 4.2937 4.3380 4.3823 4.4267 4.4710 4.5154 4.5597 4.6039 4.6480 VOUTIDEAL (V) 0.5000 0.9000 1.3000 1.7000 2.1000 2.5000 2.9000 3.3000 3.7000 4.1000 4.5000 V/V V VOUT ERROR (%FSR) 0 -0.03464537 -0.04667445 -0.04126142 -0.02381898 1.1102E-14 0.02430134 0.04294918 0.04956629 0.03753519 2.2204E-14 +0.110667 172.117 V/V V/V VALUE 0 100 0.005 +0.025 (+0.025 = +2.5%) 4.5 0.5 5 0.83 UNITS psi psi V/V % V V V
In each end application, the linearization circuit limits should be checked for operation within the allowed range. Table 15 and Table 16 illustrate the linearization range for several typical system applications. These tables account for the internal limits of the PGA309 linearization circuit and assume that VOUT scaling is to account for over-scale and under-scale limits and fault detection. For specific end applications not listed, the following equations may be used to calculate critical design values, once the system design choices for VREF, VOUT MAX,VOUT MIN and linearization range, are made: 1. VEXC MAX: Use Equation (6) at VOUT MAX 2. VEXC MIN: Use Equation (6) at VOUT MIN 3. BV MAX: (maximum compensatable nonlinearity) Use KLIN +MAX to calculate +BV MAX and KLIN -MAX to calculate -BV Max by Equation (3) solved for Bv as:
B V :+ VOUT MAX * VOUT MIN
4@V REF@K EXC K LIN
KP 0.0000 0.1090 0.2160 0.3210 0.4240 0.5250 0.6240 0.7210 0.8160 0.9090 1.0000
) 2 @ VOUT MAX ) VOUT MIN
(12)
4. VLinDAC Max = ((VREF/4) - VOUTMAX/10) > 300mV 5. VEXC Max < VSA - 0.1V 6. KLIN < KLIN MAX (LinDAC range) When using the Linearization Loop, care should be taken to ensure that the bridge sensor output common-mode voltage remains within the PGA309 input specifications. Equation (6) can be used to calculate the VEXC at full-scale signal (VOUTMAX). The common-mode voltage of the bridge sensor output is one-half of VEXC if no common-mode or temperature sensing additional resistor is used in series with the bridge sensor. During the sensor calibration process using the PGA309, a two-step process can be employed. First, the nonlinearity of the sensor bridge is measured with an initial gain and offset and with KLIN = 0 (LinDAC set to Zero). Using the resulting sensor nonlinearity (BV), values for KLIN, Gain, and Offset are calculated. A second calibration measurement can be taken to adjust KLIN, to account for any offsets and mismatches in the linearization circuitry. This calibration procedure is most easily performed using the PGA309 Designer's Kit and associated software and calibration spreadsheets.
0.05 0.04 0.03 VOUT Error (% FSR) 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 0 10 20 30 40 50 60 70 80 90 100 Pressure (psi)
Figure 29. Parabolic Bridge Corrected Nonlinearity vs Pressure
38
PGA309
www.ti.com SBOS292 - DECEMBER 2003
RANGE 0 +BV MAX ADC REF (V) 2.5 2.048 2.5 4.096 2.048 4.5 5 +BV (0.025= 2.5%) 0.0374 0.0305 0.0231 0.0371 0.0191 0.0396 0.0396 -BV (-0.025= -2.5%) -0.0454 -0.0354 -0.0259 -0.0447 -0.0210 -0.0483 -0.0483 RANGE 0 -BV MAX RANGE 0 LinDAC MAX > 0.3V? (V) 0.4025 0.4489 0.8065 0.6676 0.8458 0.7065 0.785
VSA MIN (V) 2.7 2.7 4.5 4.5 4.5 4.7 5
VSA MAX (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5
VREF (V) 2.5 2.5 4.096 4.096 4.096 4.5 5
VOUT MIN (V) 0.175 0.123 0.175 0.246 0.143 0.27 0.3
VOUT MAX (V) 2.225 1.761 2.175 3.564 1.782 4.185 4.65
VEXC MAX (V) 2.444 2.367 3.761 3.991 3.695 4.430 4.922
VEXC MIN (V) 2.104 2.095 3.429 3.441 3.423 3.780 4.200
G 167.73 138.38 106.36 166.26 88.70 176.76 176.76
VEXC MAX (V) 2.046 2.055 3.371 3.359 3.376 3.690 4.100
VEXC MIN (V) 1.706 1.783 3.039 2.808 3.104 3.040 3.378
G 240.38 183.77 131.64 236.32 105.61 257.54 257.54
PGA309 VSA Operating Range
PGA309 VREF
System ADC REF (ADC full-scale)
PGA309 VOUT Linear Range
PGA309 (+BV MAX)
PGA309 VEXC Range (+BV MAX)
PGA309 Gain VOUT/VDIFF IN (+BV MAX)
PGA309 (-BV MAX)
PGA309 VEXC Range for (-BV MAX)
PGA309 Gain PGA309 VOUT/VDIFF IN LinDAC Max (-BV MAX) Check
Assumes: 1) Over-scale and under-scale limits and fault detection desired. 2) FSS used to calculate a representative gain value (G) for completeness.
NOTE: Range 0, KEXC = 0.83, KLIN -MAX = -0.166, KLIN +MAX = 0.166, FSS = 0.005V/V
Table 15. Range 0--Typical System Applications and Maximum Nonlinearity Correction
RANGE 1 +BV MAX ADC REF (V) 2.5 2.048 2.5 4.096 2.048 4.5 5 +BV (0.025= 2.5%) 0.0439 0.0358 0.0272 0.0435 0.0226 0.0464 0.0464 -BV (-0.025= -2.5%) -0.0552 -0.0429 -0.0312 -0.0543 -0.0253 -0.0588 -0.0588 RANGE 1 -BV MAX RANGE 0 LinDAC MAX > 0.3V? (V) 0.4025 0.4489 0.8065 0.6676 0.8458 0.7065 0.785
VSA MIN (V) 2.7 2.7 4.5 4.5 4.5 4.7 5
VSA MAX (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5
VREF (V) 2.5 2.5 4.096 4.096 4.096 4.5 5
VOUT MIN (V) 0.175 0.123 0.175 0.246 0.143 0.27 0.3
VOUT MAX (V) 2.225 1.761 2.175 3.564 1.782 4.185 4.65
VEXC MAX (V) 1.576 1.518 2.400 2.572 2.351 2.859 3.177
VEXC MIN (V) 1.322 1.315 2.152 2.160 2.148 2.373 2.637
G 260.17 215.76 166.69 258.02 139.44 273.88 273.88
VEXC MAX (V) 1.278 1.285 2.108 2.099 2.112 2.307 2.563
VEXC MIN (V) 1.024 1.082 1.860 1.688 1.909 1.821 2.023
G 400.35 302.87 215.03 393.13 171.72 429.97 429.97
PGA309 VSA Operating Range
PGA309 VREF
System ADC REF (ADC full-scale)
PGA309 VOUT Linear Range
PGA309 (+BV MAX)
PGA309 VEXC Range (+BV MAX)
PGA309 Gain VOUT/VDIFF IN (+BV MAX)
PGA309 (-BV MAX)
PGA309 VEXC Range (-BV MAX)
PGA309 Gain PGA309 VOUT/VDIFF IN LinDAC Max (-BV MAX) Check
Assumes: 1) Over-scale and under-scale limits and fault detection desired. 2) FSS used to calculate a representative gain value (G) for completeness.
NOTE: Range 1, KEXC = 0.52, KLIN -MAX = -0.124, KLIN +MAX = 0.124, FSS = 0.005V/V
Table 16. Range 1--Typical System Applications and Maximum Nonlinearity Correction
39
PGA309
www.ti.com SBOS292 - DECEMBER 2003
TEMPERATURE MEASUREMENT The center of the PGA309 temperature measurement circuitry is the Temp ADC. The Temp ADC and its associated PGA, input mux, and REF mux provide a flexible and configurable temperature sensing block for reading either on-chip or external temperatures. Figure 30 illustrates the PGA309 temperature sense block. The internal temperature sensing is accomplished by using on-chip diode junctions. The Internal Temperature Sensor mode is configured through
setting the bits in Register 6 to the values shown in Table 17 and Table 18. The Temp ADC output can be read from Register 0 and is 12-bit + sign extended, right-justified, Two's Complement data format for R1 and R0 = `11', and TEN = `1' (see Table 19). For this Temp ADC resolution, the typical measured temperature resolution is 0.0625C and the accuracy is 2C. The temperature accuracy is a relative error that is calibrated out with the PGA309 + sensor calibration to the accuracy of the calibration temperature measurement equipment.
REFIN/REFOUT
VREF INT/EXT Select VSA Temp ADC Internal VREF (2.048V) Temp ADC REF Mux VREF VEXC VSA Temp ADC REF Select VREF Internal Set (2.5V or 4.096V) RFB VREF Bandgap Reference
ITEMP 7A INT Temperature (on- chip diodes)
I TEMP Enable TEMPIN VREF VEXC VOUT
TEMPIN
VREFT Temp ADC Input Mux
R SET
xG
15- + Sign Bit ADC Temperature Source Select
Digital Controls Control Registers Alarm Register Interface and Control Circuitry SDA SCL
Temp ADC Input Mux Select
Temp ADC PGA (X1, X2, X4, X8)
Offset TC Adjust and Span TC Adjust Lookup Logic with interpolation Algorithm
PRG
PGA309 Temperature Sense Block
Figure 30. Temperature Sense Block
40
PGA309
www.ti.com SBOS292 - DECEMBER 2003 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BIT NAME RFB RFB ADC2X ADCS ISEN CEN TEN AREN RV1 RV0 M1 M0 G1 G0 R1 R0 BIT STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 See Temp ADC Resolution (Conversion time); select below See Temp ADC Resolution (Conversion time); select below Unused for Internal Temperature Mode; set to zero. Enable the Temp ADC Internal Temperature mode selected Unused for Internal Temperature Mode; set to zero. CONFIGURATION Reserved Factory Bit--set to zero for proper operation Reserved Factory Bit--set to zero for proper operation
Table 17. Internal Temperature Mode Configuration--Register 6
TEMP ADC RESOLUTION (CONVERSION TIME) SELECT TEN = `1' 9-Bit + Sign, Right-Justified, Sign-Extended, 0.5C (3ms) 10-Bit + Sign, Right-Justified, Sign-Extended, 0.25C (6ms) 11-Bit + Sign, Right-Justified, Sign-Extended, 0.125C (12ms) 12-Bit + Sign, Right-Justified, Sign-Extended, 0.0625C (24ms)
R1 0 0 1 1
R0 0 1 0 1
Table 18. Temperature Mode Resolution--Register 6
TEMPERATURE (C) 128 127.9375 100 80 75 50 25 0.25 0.0 -0.25 -25 -55 -128 DIGITAL OUTPUT (BINARY) AD15............AD0 0000 1000 0000 0000 0000 0111 1111 1111 0000 0110 0100 0000 0000 0101 0000 0000 0000 0100 1011 0000 0000 0011 0010 0000 0000 0001 1001 0000 0000 0000 0000 0100 0000 0000 0000 0000 1111 1111 1111 1100 1111 1110 0111 0000 1111 1100 1001 0000 1111 1000 0000 0000 DIGITAL OUTPUT (HEX) 0800 07FF 0640 0500 04B0 0320 0190 0004 0000 FFFC FE70 FC90 F800
There are several optional configurations possible for the Temp ADC when External Temperature Sensor mode is selected. In this mode, the TEMPIN pin is being read as an indication of temperature. TEMPIN may be referenced to GND, VEXC, or VREF. In addition, VOUT may also be selected to be read relative to GND through the Temp ADC. Figure 31 shows the allowed Temp ADC input mux configurations. Note that the choice to read VOUT will result in reading the VOUT pin of the PGA309 and not the VFB pin. This will be a different voltage than the final conditioned sensor output at VFB in applications that use an RISO resistor for overvoltage output protection and capacitive load isolation (see Output Amplifier section for details).
Table 19. Internal Temperature Mode--Data Format (12-Bit Resolution)--Register 0
41
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Temp ADC Input Mux Configuration #1 Register 6[5:4] = '00' (default) Register 6[M1,M0] = '00' (default) Positive Input TEMPIN
GNDA
The temperature sense block also contains an 7A (typ) current source that is enabled by a logic `1' written to Register 6, bit 11, ISEN. A logic `0' disables ITEMP from the TEMPIN pin. This current source can be used to excite an external resistive temperature device or diode for bridge sensor temperature measurement, as shown in Figure 32.
Negative Input Temp ADC PGA
Temp ADC Input Mux Configuration #2 Register 6[5:4] = '01' Register 6[M1,M0] = '01' Positive Input VEXC TEMPIN Negative Input Temp ADC PGA TEMPIN
VSA
PGA309 I TEMP Block
ITEMP 7A
ITEMP Enable TEMPIN VREF _C VEXC VOUT
Temp ADC Input Mux Configuration #3 Register 6[5:4] = '10' Register 6[M1,M0] = '10' Positive Input VOUT
Temp ADC Input Mux
GNDA
Negative Input Temp ADC PGA
Temp ADC Input Mux Select
Temp ADC Input Mux Configuration #4 Register 6[5:4] = '11' Register 6[M1,M0] = '11' Positive Input VREF TEMPIN Negative Input Temp ADC PGA
Figure 32. ITEMP for External Temperature Measurement The Temp ADC has several choices for its reference voltage for analog-to-digital conversions when used in External Temperature mode; these are illustrated in Table 21. In addition, the resolution of the Temp ADC when used in External Temperature mode is also register-selectable (see Table 22).
AREN [8] 0 RV1 [7] 0 0 1 1 X RV0 [6] 0 1 0 1 X TEMP ADC REFERENCE (VREFT) VREF VEXC VSA Factory Reserved Temp ADC Internal REF (2.048V)
Figure 31. Temp ADC Input Mux Options The Temp ADC PGA has four available gain settings that are detailed in Table 20.
G1 [3] 0 0 1 1 G0 [2] 0 1 0 1 TEMP ADC PGA GAIN X1 X2 X4 X8
0 0 0 1
NOTE: X = don't care.
Table 20. Temp ADC PGA Gain Select--Register 6
Table 21. Temp ADC Reference Select--Register 6
42
PGA309
www.ti.com SBOS292 - DECEMBER 2003 R1 [1] 0 0 1 1 R0 [0] 0 1 0 1 EXTERNAL SIGNAL MODE [TEN=0], EXTERNAL REFERENCE [AREN=0] 11-Bit + Sign, Right-Justified, Sign-Extended (6ms) 13-Bit + Sign, Right-Justified, Sign-Extended (24ms) 14-Bit + Sign, Right-Justified, Sign-Extended (50ms) 15-Bit + Sign, Right-Justified, Sign-Extended (100ms) EXTERNAL SIGNAL MODE [TEN=0], INTERNAL REFERENCE [2.048V, AREN=1] 11-Bit + Sign, Right-Justified, Sign-Extended (8ms) 13-Bit + Sign, Right-Justified, Sign-Extended (32ms) 14-Bit + Sign, Right-Justified, Sign-Extended (64ms) 15-Bit + Sign, Right-Justified, Sign-Extended (128ms)
Table 22. Temp ADC Resolution (Conversion time)--Register 6 Temp ADC Start-Convert Control The Temp ADC has two conversion modes: Single and Continuous. In Continuous Conversion mode (CEN = `1'), the Temp ADC initiates the next conversion cycle immediately after a conversion is complete. In Single Conversion mode (CEN = `0') the Temp ADC start-convert bit (ADCS) acts as a start-convert/busy bit and must be written or set to `1' before a conversion is initiated. After a `1' is written to ADCS, it will be a `1' if read immediately and can be polled until it returns to a `0', indicating the conversion is complete. The Start-Convert modes allowed are shown in Table 23. In Figure 33 continuous start-convert control is selected. After an initial power-on reset timeout of typically 25ms, the register configuration (part one) of
CEN [10] 0 0 1 ADCS [12] 0 1 X CONVERSION MODE Single Single Continuous
the EEPROM is read. Immediately after this, a Temp ADC conversion is started. At the end of this first conversion, the temperature coefficients (part two) of the EEPROM are read, and Zero and Gain DAC settings are adjusted. When CEN = `1', then at the end of each conversion another conversion is started. When the temperature coefficients are through being read, the EEPROM is read again at the beginning where the register configuration values are stored. Note that the only ADC results that are used to trigger the reading of the second half of the EEPROM (temperature coefficients) are the ones after a valid register configuration read part of the EEPROM. This operation yields the most temperature updates over a given time period.
COMMENTS Temp ADC in standby mode - no conversions. Temp ADC starts conversion and ADCS acts as busy bit with it changing to a `0' at end of conversion. ADCS bit exercises no control - typically ADCS =`1' since conversions are continuous.
Table 23. Temp ADC Start-Convert Control--Register 6
Internal or External Temperature Mode TEN = '0', CEN = '0', ADCS = 'x' (don't care)
VOUT EEPROM Read
Disabled
Enabled
Reg Config and Checksum1
Temp Coeff and Checksum2
Reg Config and Checksum1
Temp Coeff and Checksum2
Reg Config and Checksum1
Temp ADC Start Conversion Temp ADC End Conversion
Initial POR Conversion
t0 t = 25ms
ADC Results Ignored ADC Results Used for Zero and Gain DAC Update Based on Temp Coefficient
ADC Results Ignored
ADC Results Used for Zero and Gain DAC Update Based on Temp Coefficient
Figure 33. Temp ADC Continuous Start-Convert Control
43
PGA309
www.ti.com SBOS292 - DECEMBER 2003
In Figure 34, single start-convert control is selected. After an initial power-on reset timeout of typically 25ms, the register configuration (part one) of the EEPROM is read. Immediately after this, a Temp ADC conversion is started if CEN = `0' and ADCS = `1'. At the end of this first conversion, the temperature coefficients (part two) of the EEPROM are read, and Zero and Gain DAC settings are adjusted. When CEN = `0' and ADCS = `1', a new start conversion only occurs after reading the register configuration part of the EEPROM. At the end of this conversion, the second part of the EEPROM (temperature coefficients) is read, the Gain and Zero DAC temperature calculations are done, and each respective DAC updated. Note that in the Single Start-Convert mode, if CEN = `0' and ADCS = `0' (no Temp ADC conversions), the PGA309 will wait 25ms after power-on, read the register configuration part of
the EEPROM, and without an ADC conversion, read the Lookup Table and calculate Gain and Zero DAC values. These values are based on the current ADC output register (all zero). The PGA309 output will then be enabled and will wait about 25ms, and read the register configuration part of the EEPROM. The output remains enabled with a continuous loop of reading the register configuration part of the EEPROM, waiting 25ms, and back to reading again. One final control option for External Temperature mode is the ADC2X bit, Register 6 bit [13]. This bit allows the conversion speed of the Temp ADC to be increased for external temperature readings only. Table 24 shows the typical settings and the effect of the ADC2X bit.
Internal or External Temperature Mode TEN = '0', CEN = '0', ADCS = '1'
VOUT
Disabled
Enabled
EEPROM Read
Reg Config and Checksum1
Temp Coeff and Checksum2
Reg Config and Checksum1
Temp Coeff and Checksum2
Temp ADC Start Conversion Temp ADC End Conversion
Initial POR Conversion
ADC Idle t0 t = 25ms
ADC Results Used for Zero and Gain DAC Update Based on Temp Coeff
ADC Results Used for Zero and Gain DAC Update Based on Temp Coeff
Figure 34. Temp ADC Single Start-Convert Control
[TEN=0], [AREN=0], [ADC2X=0] 11-Bit + Sign (6ms) 13-Bit + Sign (24ms) 14-Bit + Sign (50ms) 15-Bit + Sign (100ms) [TEN=0], [AREN=0], [ADC2X=1] 11-Bit + Sign (3ms) 13-Bit + Sign (12ms) 14-Bit + Sign (25ms) 15-Bit + Sign (50ms) [TEN=0] [2.048V, AREN=1], [ADC2X=0] 11-Bit + Sign (8ms) 13-Bit + Sign (32ms) 14-Bit + Sign (64ms) 15-Bit + Sign (128ms) [TEN=0] [2.048V, AREN=1], [ADC2X=1] 11 Bit + Sign (4ms) 13 Bit + Sign (16ms) 14 Bit + Sign (32ms) 15 Bit + Sign (64ms)
R1 [1] 0 0 1 1
R0 [0] 0 1 0 1
Table 24. Temp ADC Conversion Speed Options for External Temperature Mode
44
PGA309
www.ti.com SBOS292 - DECEMBER 2003
External Temperature Sensing with an Excitation Series Resistor For some bridge sensor applications, it is desired to measure the temperature of the bridge sensor by the change in the bridge resistance. This is accomplished by adding a series resistor in either the top or the bottom of the bridge excitation connections. When this is done, the common-mode voltage range of the PGA309 inputs must be observed over the operating temperature range of the application. Figure 35 shows a top-side series resistor used to monitor the change in bridge resistance with temperature. For simplification of analysis, the effective bridge resistance is converted to one resistor (RBT), as shown. For a given temperature, RBT will be a fixed value; 1.8k for this example at 70C. Since RT has a negligible change in temperature (50ppm/C) compared with RBT (3500ppm/C), RT is used to detect a change in RBT. For this application, the Temp PGA is configured for VEXC on the +input, and TEMPIN on the -input. The Temp ADC uses VEXC as its reference, VREFT. The PGA gain is set to X8. Notice that two different values for VEXC will be analyzed to emulate the changing voltage on VEXC due to the linearization block adjusting VEXC to minimize error on the bridge sensor output with applied pressure. The square-boxed values show numerical results for VEXC = 2.9V and the oval-ringed values for VEXC = 2.4V. The final Temp ADC
reading will be the same value as shown relative to full-scale range. This is equivalent to the same digital output of the Temp ADC regardless of what value VEXC is adjusted to by the linearization block. Figure 36 shows a bottom-side series resistor used to monitor the change in bridge resistance with temperature. Again, for simplification of analysis, the effective bridge resistance is converted to one resistor, RBT, as shown. For 70C, RBT will be 1.8k for this example. RT will be used to measure the change in RBT. The Temp PGA is configured for TEMPIN on the +input and GND on the -input. VEXC is selected as the Temp ADC reference, VREFT. The PGA gain is X8. The square-boxed values are results for VEXC = 2.9V and the oval-ringed values for VEXC = 2.4V. It is seen that the final Temp ADC reading will be the same regardless of the VEXC value. If the linearization block is not used in the application, the bridge sensor top excitation connection is either connected to VSA or VREF instead of VEXC. In either of these cases, top-side (Figure 35) or bottom-side (Figure 36), external temperature sensing can be done by adding a series resistor, RT. The Temp ADC reference (VREFT) should be changed to the bridge excitation voltage (VSA or VREF) for the specific application. This yields a constant Temp ADC output at a given temperature independent of changes in the bridge excitation voltage.
PGA309 External Temperature Mode 2.9V 2.4V RT 100 2.747368421V 2.273684211V TEMPIN Temp PGA X8 VREFT Temp ADC Temp ADC Out (% Full-Scale Range) VEXC VEXC Linearization Block VREF VFB 2.9V VEXC 2.4V
RB
RBT _C 1.8k at 70_C
0.152631579V 0.126315789V
1.221052632V 1.010526316V
42.1052631% 42.1052631%
Figure 35. External Temperature Sensing of Bridge Sensor with Top-Side Series Resistor
45
PGA309
www.ti.com SBOS292 - DECEMBER 2003
2.9V 2.4V VEXC VEXC PGA309 External Temperature Mode
Linearization Block
VREF VFB VEXC 2.4V 2.9V
RB
RBT _C 1.8k at 70_C TEMPIN Temp PGA X8 RT 100
VREFT Temp ADC Temp ADC Out (% Full-Scale Range)
0.152631579V 0.126315789V
1.221052632V 1.010526316V
42.1052631% 42.1052631%
Figure 36. External Temperature Sensing of Bridge Sensor with Bottom-Side Series Resistor OUTPUT AMPLIFIER The Output Amplifier section of the PGA309 is configured to allow maximum flexibility and accuracy in the end application. Figure 37 depicts the output amplifier in a common three-terminal sensor application. In this application, it is desired to provide overvoltage protection due to mis-wires on the output of the PGA309, as well as a 10nF capacitor on the sensor module output for EMI/RFI filtering. In this configuration, RISO and RFB provide overvoltage protection on VOUT FILT to 16V by limiting the current into VOUT and VFB to about 150mA [(16V - 0.7V)/100]. The 0.7V drop being the internal ESD structure to GND or VSA. In addition, RISO serves to isolate the 10nF RFI/EMI capacitive load from VOUT. RFB adds a slight gain error that is calibrated out with the PGA309 + sensor calibration. Note that the point of feedback around the output amplifier is taken from VOUT FILT and as such, after PGA309 + sensor calibration, the output amplifier will accurately scale VOUT FILT to match the desired conditioned sensor voltage. CF provides a second feedback path around the output amplifier for guaranteed stability. With the configuration shown, the output amplifier is stable for internal output amplifier gains from X2 (125kHz bandwidth, 63 loop gain phase margin, typical values) to X9 (64kHz bandwidth, 86 loop gain phase margin, typical values). Table 25 details the typical output amplifier resistor values for RFO and RGO, as well as open-loop output resistance. These values, combined with the typical output amplifier open-loop gain curve and standard op amp stability techniques, allow the output amplifier to be tailored and configured for the specific sensor application.
RFO TYPICAL (k) 18 21 24 26 28 30 32 RGO TYPICAL (k) 18 15 12 10 8 6 4
GAIN X2 X2.4 X3 X3.6 X4.5 X6 X9
NOTE: RO = open-loop output resistance = 675, typical at 1MHz.
Table 25. Output Amplifier Typical Gain Resistor Values
46
PGA309
www.ti.com SBOS292 - DECEMBER 2003
VSA
VSD SDA SCL Two-Wire EEPROM
PGA309 Output Amplifier
Interface and Control Circuitry
PRG Front-End PGA Out Fine Gain Adjust (Gain DAC) Output Amp VOUT ~150mA
VS RISO 100 VOUT FILT 16V Mis-Wire Fault Condition
INT/EXT FB Select RFO Output Gain Select (1-of-7) Range of 2 to 9 VFB
~150mA
R FB 100 CL 10nF
GND
RGO VSJ
CF 150pF
Shows current in case of output mis-wiring or overvoltage.
GNDA
GNDD
Figure 37. Output Amplifier in a Common 3-Terminal Sensor Application In addition to using its own internal gain setting resistors, RFO and RGO, the output amplifier may use external feedback resistors RFOEXT and RGOEXT, as shown in Figure 38. Table 26 details the bits used in Register 4 for the desired output amplifier gain configurations. To use the external feedback resistors, set GO2, GO1, and GO0 to all 1s. In addition to allowing external feedback resistors to be used, this configuration provides a handy mechanism for testing the output amplifier stability, even if internal gain settings are to be used. As shown in Figure 38, external feedback resistors RFOEXT and RGOEXT are both set to 18k, equivalent to the typical resistor values used for an internal gain setting of X2. If VOUT is biased up to mid-scale (+2.5V for VSA = +5V), a signal generator may be used to inject a 200mVPP square wave (1kHz) into the end of RGOEXT and a response measured at VOUT. This provides a transient response for the output amplifier in a given configuration. Standard stability transient response criteria for a dominant two-pole system may be used to determine suitable phase margin based upon the measured overshoot and ringing on VOUT.
GO2 [14] 0 0 0 0 1 1 1 1 GO1 [13] 0 0 1 1 0 0 1 1 GO0 [12] 0 1 0 1 0 1 0 1
OUTPUT AMPLIFIER GAIN 2 2.4 3 3.6 4.5 6 9 Disable Internal Feedback
Table 26. Output Amplifier Gain Selections--Register 4
47
PGA309
www.ti.com SBOS292 - DECEMBER 2003
VOUT VSA VSD SDA t SCL Two-Wire EEPROM
PGA309 Output Amplifier
Interface and Control Circuitry
PRG Front-End PGA Out Fine Gain Adjust (Gain DAC) Output Amp VOUT
VS RISO 100 VOUT FILT CL 10nF GND RFOEXT 18k
INT/EXT FB Select RFO Output Gain Select (1-of-7) Range of 2 to 9 VFB
R FB 100
RGO VSJ
CF 150pF
GNDA
GNDD
RGOEXT 18k VTEST +100mV -100mV f = 1kHz
Figure 38. Output Amplifier Using External Feedback Resistors RFOEXT and RGOEXT For low-supply applications, the minimum gain for the output amplifier is related to its input voltage range and output voltage swing. In Figure 39, the supply is lowered to +2.7V. The tested input voltage range of the output amplifier is 0V to VSA-1.5V, as reflected in Figure 39. The output voltage swing is tested to be 0.1V to +2.6V for a 10k load, as shown. This calculates to a minimum gain of X2.08. For best performance, the output amplifier should be scaled for a minimum gain of X2.4 for this application. Usually, this is only a factor at lower voltages but is easily checked for each individual application.
+1.2V IVR 0V VIN+
VSA +2.7V +2.6V VIN+ +0.1V RGO RFO
Output Amplifier Gain Minimum = VOUT/VIN+ = +2.5V/+1.2V = X2.08 Use X2.4
Figure 39. Output Amplifier Minimum Gain at Low Supply
48
PGA309
www.ti.com SBOS292 - DECEMBER 2003
GENERAL AC CONSIDERATIONS In addition to normal good analog layout and design practices, there are a few key items to check when designing with the PGA309. 1. REFIN/REFOUT, pin 16: Keep capacitive loading to 200pF or less. 2. VEXC, pin 1: Keep capacitive loading to 200pF or less. 3. VSA, pin 3 and VSD, pin 10: Keep these within 200mV of each other. Internally, the PGA309 separates its digital and analog power supplies to minimize cross-talk between the two. Externally, tie the two together and bypass, directly at the pins, with a 0.1F capacitor. If an RC filter is used between the two supplies, ensure that maximum drop is never more than 200mV. 4. GNDA, pin 2 and GNDD, pin11: Ensure that these are both tied directly together and connected to the same ground point. 5. VSJ, pin 8: This is the negative input to the output amplifier and as such, it is high-impedance. Route low-impedance traces, such as VOUT, and noisy
traces away from VSJ. Minimize trace lengths to avoid unwanted additional capacitance on VSJ. 6. VIN1, pin 4 and VIN2, pin 5: For source resistances greater than or equal to 10k, add a capacitor of 1nF to 2nF between VIN1 and VIN2 to minimize noise coupling. 7. VIN1, pin 4 and VIN2, pin 5: RFI filtering is always a concern for instrumentation amplifier applications. RFI signals injected into instrumentation amplifiers become rectified and appear on the output as a DC drift or offset; high-gain circuits amplify this effect. Figure 40 depicts input filtering for the PGA309. Depending upon the distance of the bridge sensor from the PGA309 and the sensor module shielding, R1 and R2 may be required. C1 should be equal to C2, and C3 should be ten times larger than C1 to attenuate any common-mode signals that become differential due to the mismatch in C1 and C2. All input filter components should be located directly at the PGA309 inputs to avoid and trace lengths from becoming receiving RFI antennas.
VEXC
R1
VIN1 C1 C3(2) Mux Front- End PGA
(1)
R2
C2 VIN2 PGA309
(1)
NOTES: (1) Depends on bridge sensor resistance and distance from bridge sensor to PGA309. (2) C1 = C2, C3 = 10 x C1.
Figure 40. Input Filtering
49
PGA309
www.ti.com SBOS292 - DECEMBER 2003
OPERATING MODES Power-On Sequence and Normal Stand-Alone Operation The PGA309 internal state machine controls the operations of the part in stand-alone mode, without any external digital controller. In this mode, the PGA309 performs the functions of a Two-Wire interface master to read the data from the EEPROM. The PGA309 has power-on reset (POR) circuitry to reset the internal registers and subcircuits to their initial states. This power-on reset also occurs when the supply is detected to be too low so that the PGA309 is in a known state when the supply becomes valid again. The threshold for the POR circuit is approximately +1.5V to +2.5V. After the power supply becomes valid, the PGA309 waits for approximately 25ms and then attempts to read the configuration register data (Register 3--Register 6 bit settings) from the first 16 bytes of the external EEPROM device. If the EEPROM has the proper programmed flag word (0x5449, "TI" ASCII) in address locations 0 and 1, the PGA309 will continue reading the EEPROM. Otherwise, the PGA309 will wait for one second before trying again. If the PGA309 detects that there was no response from the EEPROM and the Two-Wire bus was in a valid idle state (SCL = `1', SDA = `1'), then the PGA309 will wait for 1s and try again. If the Two-Wire bus is stuck with SDA = `0', the PGA309 will try to free the bus by sending extra clocks down SCL (see the Digital Interface section for details), and wait for 25ms before trying to read the EEPROM again. If the EEPROM configuration read is successful (including valid Checksum1 data) and either bits ADCS or CEN in Register 6 are set to `1', the PGA309 will trigger the Temp ADC to measure the temperature information as configured in the configuration registers. For 16-bit resolution results, the converter takes approximately 125ms to complete a conversion. Once the conversion is complete, the PGA309 begins reading the Lookup Table from EEPROM address locations 16 and higher, to calculate the settings for the Gain and Zero DACs using the piecewise linear interpolation algorithm. The PGA309 reads the entire Lookup Table and determines if the checksum for the Lookup Table
(Checksum2) is correct. Each entry in the Lookup Table requires approximately 500s to read from the EEPROM. Once Checksum2 is determined to be valid, the calculated value for the Gain and Zero DACs is updated into their respective registers, and the output amplifier (VOUT) is enabled. The PGA309 then begins looping through this entire procedure, starting again with reading the configuration data from the first part of the EEPROM. This loop continues indefinitely.
NOTE: During the entire initial power-on sequence, the PGA309 VOUT is disabled (high-impedance) until valid EEPROM contents are verified and an ADC conversion is complete, as described above and illustrated in Figure 41. If the the PGA309 is used in a true three-wire connection (VS, GND and VOUT with PRG pin shorted to VOUT) the time interval after power-up is the only opportunity that an external communications controller can initiate digital communication with the PGA309 and trigger a one second delay in the internal state machine. After VOUT is enabled no further digital communication is possible.
If the PGA309 detects that there is no EEPROM device present (that is, it does not receive an acknowledge to a slave address byte sent to the EEPROM), the PGA309 will wait for approximately one second and try again. It will continue in this loop indefinitely with VOUT disabled. At any time, if the PGA309 is addressed through the Two-Wire or One-Wire interface, the internal state machine aborts its cycle and initiates a 1s delay. After the 1s delay has timed out, a EEPROM read is started. The 1s delay is reset every time the PGA309 is addressed. This allows an external microcontroller to control the function of the PGA309, as long as some communication activity is addressed to the PGA309 at least once per second. VOUT will stay in the state (enabled or disabled) that it was in before the PGA309 was addressed. If full microcontroller control of the PGA309 is desired from initial power-on, then the Test pin should be brought high to enable the output after the internal PGA309 registers have been configured to their desired state.
50
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Power- On
Disable VOUT
Power Valid ? Yes Wait 25ms
No
Begin EEPROM Read
Wait 1 second No
EEPROM Acknowledge ? Yes
No
Two- Wire Bus Stuck
Yes
Try to Free Two- Wire Bus
Wait 1 second
No
Programmed Flag Values Correct ? Yes Read First Part of EEPROM
No
Start Temp ADC Single Conversion
125ms Delay (16- Bit resolution) Read Second Part of EEPROM
Temp ADC Continuous Conversion (CEN = '1') ?
Yes
Wait for Conversion Complete
Wait 25ms
Yes ADCS = '1' or CEN = '1' ?
No No
Checksum2 Correct ? Yes Update Gain and Zero DACs
Disable VOUT
No
Checksum1 Correct ? Yes Set Configuration Registers to EEPROM Values
Wait 25ms
Set Gain and Zero DACs to POR Values
Enable VOUT
Figure 41. State Machine--Power-On Sequence and Operation in Stand-Alone Mode
51
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Checksum Error Event If at any time the PGA309 detects an invalid Checksum1 from the first part of the EEPROM, the PGA309 will disable VOUT, wait for approximately 25ms, and try to read the EEPROM again from the beginning. It will continue to re-read the EEPROM indefinitely. If at any time the PGA309 detects an invalid Checksum2 from the second part of the EEPROM (the Lookup Table data), it will disable VOUT, set the Gain and Zero DACs to their POR values, return to the read configuration register portion (first part of the EEPROM) of the loop, and then try to read the EEPROM Lookup Table again when the next temperature conversion completes. Test Pin The PGA309 has a user-accessible test pin (Test, pin 9), which stops the internal state machine cycle and enables the output drive (VOUT) when it is brought high (logic `1'). This mode can be used for ease of troubleshooting or initial configuration diagnostics during the system design. During normal (stand-alone) operation, the Test pin must be pulled or shorted to GND (logic `0'). If the Test pin is pulled high at any time, the following happens:
Table 27 summarizes the key settings for the POR states.
PARAMETER Coarse Offset Front-End PGA Gain Gain DAC Output Amplifier Gain Zero DAC VREF Select Lin DAC Fault Monitor Over/Under-Scale VEXC ITEMP Temp ADC POR STATE 0V X4 (VIN1 = VINP, VIN2 = VINN) X0.5 X2 0.25VREF External Reference X0 Disabled Disabled Disabled Disabled External Signal Mode
Table 27. POR States for Key Parameters
+5V +5V SDA Two- Wire EEPROM SCL PRG VOUT +5V 1k VIN2
RTEST = 0 VDIFF = 0V RTEST = 0 VOUT = 1.25V
D The state machine described previously is
interrupted and reset to its initial state. Any EEPROM transactions are interrupted and the Two-Wire bus is released. D The PGA309 output (VOUT) is enabled. D All internal registers are kept to their current values. If the Test pin is high when the supply becomes valid, the registers stay in the initial (POR) state and output is enabled immediately. D An external controller can modify any of the writable PGA309 registers using either a One-Wire or Two-Wire digital interface. In this mode, a test signal can be applied to the front-end of the PGA309, which quickly verifies if the signal path through the PGA309 is functioning correctly. Power-On Initial Register States In a power-up or a brownout event, the POR circuit resets all the PGA309 registers to their initial state. All registers are set to zeros except for the Gain and Zero DACs, which both are set to 0x4000. Example: PGA309 Power-Up State
VSD
VSA
REFIN/REFOUT
VEXC
VOUT
RTEST = 446.5 V OUT = 4.9V
PGA309
VFB
RTEST 500
RTEST = 446.5 VDIFF = 0.9125V
VDIFF VIN1 VSJ +5V TEMPIN Test 10k
1k
GNDA
GNDD
Figure 42. Signal Path Functional Check with Test = `1' on Power-Up
For a +5V supply and configuration as shown in Figure 42 with Test pin HIGH, the gain and offset scaling through the PGA309 on power-up becomes: VOUT = VDIFF (Front-End PGA Gain)(Output Amplifier Gain)(Fine Gain) + 0.25VREF(Fine Gain)(Output Amplifier Gain) VOUT = VDIFF (4)(2)(0.5) + (0.25(5)(0.5)) x 2 VOUT = 4 VDIFF + 1.25V
52
PGA309
www.ti.com SBOS292 - DECEMBER 2003
DIGITAL INTERFACE There are two digital interfaces on the PGA309. The PRG pin uses a One-Wire, UART compatible interface, with bit rates from 4.8kbits/s (4800 baud) to 38.4kbits/s (38400 baud). The SDA and SCL pins together form an industry standard Two-Wire interface at clock rates from 1kHz to 400kHz. The external EEPROM uses the Two-Wire interface for programming and reading. Communication to the PGA309 internal registers can be conducted through either digital interface, One-Wire or Two-Wire. Additionally, the external EEPROM can be programmed through the PGA309 One-Wire interface pin, PRG. Two-Wire Interface The industry standard Two-Wire timing diagram is shown in Figure 43, with the timing diagram definitions in Table 28. The key operating states are:
D Stop Data Transfer: A change in the state of the
SDA line from low to high while the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
D Data Transfer: The number of data bytes
transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data.
D Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a not-acknowledge on the last byte that has been transmitted by the slave (see Figure 44).
D Bus Idle: Both SDA and SCL lines remain high. D Start Data Transfer: A change in the state of the
SDA line, from high to low, while the SCL line is high, defines a START condition. Each data transfer is initiated with a START condition.
tLOW
tR
tF
tHDSTA
SCL tHDSTA t HDDAT SDA tBUF P S P = STOP Condition, S = START Condition S P tHIGH t SUSTA tSUDAT tSUSTO
Figure 43. Two-Wire Timing Diagram
PARAMETER SCL Operating Frequency Bus Free Time Between STOP and START Conditions Hold Time After Repeated START Condition. After this period, the first clock is generated. Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock LOW Period SCL Clock HIGH Period Clock/Data Fall Time Clock/Data Rise Time fSCL tBUF tHDSTA tSUSTA tSUSTO tHDDAT tSUDAT tLOW tHIGH tF tR MIN 1 600 600 600 600 0 100 1300 600 300 300 MAX 400 UNITS kHz ns ns ns ns ns ns ns ns ns ns
Table 28. Two-Wire Timing Diagram Definitions
53
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Master Data Transmitted Not Acknowledge Slave Data Transmitted SCL From Master S
Acknowledge 1 2 8 9
START Condition
Figure 44. Two-Wire Acknowledge Device Addressing: Following a START condition issued by the master, a control byte is the first byte received. The seven most significant bits (MSBs) of the control byte are the slave address for the part being addressed. The last bit of the control byte is a read/write control bit (read = `1', write = `0'). The slave addresses for the PGA309 and supported external EEPROM are shown in Figure 45. One-Wire Interface The PGA309 may be configured through a single-wire UART-compatible interface (PRG pin). The interface also allows programming of the external industrystandard Two-Wire EEPROM device. There are six communication transactions that are available. These transactions allow the internal register pointer to be updated, the external EEPROM pointer to be updated, internal registers to be read, internal registers to be written, EEPROM data to be read, and EEPROM data to be written. It is possible to connect the PRG pin, which uses the One-Wire interface, to the VOUT pin in true three-wire sensor module and still allow for digital programming. Each transaction consists of several bytes of data transfer. Each byte consists of 10 bit periods. The first bit is the start bit and is always zero. The PRG pin should always be high when no communication is in progress. The one-to-zero (high-to-low) transition signals the start of a byte transfer and all timing information for the current byte is referenced to this transition. The second through ninth bits are the eight data bits for the byte and are transferred least significant bit (LSB) first. The tenth bit is the stop bit and is always one. The recommended circuit implementation is to use a pull-up resistor and/or current source with an open drain (or open collector) driver connected to the PRG pin, which is also an open drain output. The PRG pin may be driven high by the digital programmer (controller) during transmit from the controller, but some form of pull-up will be required to allow the signal to go high during receive, since the PGA309 can only pull the output low. Figure 47 shows a typical connection between the PGA309 PRG pin and the controller.
START
READ/WRITE
S
S LAV E A D D R E S S
R/W ACK
1
0
1
0
P10
P9
P8
External EEPROM Control Byte Allocation
START
READ/WRITE
S
S LAV E A D D R E S S
R/W ACK
1
0
0
0
0
0
0
PGA309 Control Byte Allocation
Figure 45. External EEPROM and Control Byte Allocation Two-Wire Access to PGA309 The read and write timing supported for interfacing directly with the PGA309 internal registers is shown in Figure 46.
54
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Write Timing: Two- Wire
Slave ID SDA S 1 0 0 0 0 0 0 R/W 0 A P 0 0 A A 0 P4 P3 P2 P1 P0 P D7 D6 D5 D4 D3 D2 D1 D0 P Register Data (8 LSBs)
D15 D14 D13 D12 D11 D10 D9 D8
A P
P
Control Byte
Register Address
Register Data (8 MSBs)
Read Timing: Two- Wire
Slave ID SDA S 1 0 0 0 0 0 0 R/W 0 A P 0 0 0 A P4 P3 P2 P1 P0 P S 1 0 Slave ID 0 0 0 0 0 R/W 1 A A P D7 D6 D5 D4 D3 D2 D1 D0 C Register Data (8 LSBs)
D15 D14 D13 D12 D11 D10 D9 D8
A C
P
Control Byte
Register Address
Control Byte
Register Data (8 MSBs)
Wire Protocol NOTES: S = START Condition of Two- P = STOP Condition of Two-Wire Protocol A = Acknowledge from Controller C A = Not Acknowledge from Controller C A = Acknowledge from PGA309 P
Figure 46. Two-Wire Access to PGA309 Timing
VS Controller VSA VSD PRG Logic and Control PGA309 GNDA GNDD RPU
Figure 47. Typical PGA309 PRG To Controller Connection All communication transactions start with an initialization byte transmitted by the controller. This byte (55h) is used to sense the baud rate used for the communication transaction. The baud rate is sensed during the initialization byte of every transaction. This baud rate is used for the entire transaction. Each transaction may use a different baud rate if desired. Baud rates of 4800 to 38400 are supported. The second byte is a command byte transmitted by the controller. There are six possible commands:
D D D D D D
Set Register Address Pointer (01h) Set EEPROM Address Pointer (02h) Write Register (04h) Write EEPROM Word (08h) Read Register (10h) Read EEPROM Word (20h) See Figure 48 for timing details of these transactions.
55
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Set PGA309 Register Address Timing
PRG S 1 0 1 0 1 0 1 0 P S 1 0 0 0 0 0 0 0 P S P0 P1 P2 P3 P4 X X X P
Initialization Byte (55h)
Register Address Command (01h)
Register Address Pointer
Write To PGA309 Register Timing
PRG S 1 0 1 0 1 0 1 0 P S 0 0 1 0 0 0 0 0 P S D0 D1 D2 D3 D4 D5 D6 D7 P Register Data (8 LSBs) S D8 D9
D10 D11 D12 D13 D14 D15
P
Initialization Byte (55h)
Register Write Command (04h)
Register Data (8 MSBs)
Read From PGA309 Register Timing
PRG S 1 0 1 0 1 0 1 0 P S 0 0 0 0 1 0 0 0 P One- Byte Period Delay Allows for Bus Direction Change
Driven by PGA309 S D0 D1 D2 D3 D4 D5 D6 D7 P Register Data (8 LSBs) S D8 D9
D10 D11 D12 D13 D14 D15
P
Initialization Byte (55h)
Register Read Command (10h)
Register Data (8 MSBs)
Set EEPROM Address Timing
PRG S 1 0 1 0 1 0 1 0 P S 0 1 0 0 0 0 0 0 P S P0 P1 P2 P3 P4 P5 P6 P7 P S P8 P9
P10
X
X
X
X
X
P
Initialization Byte (55h)
EEPROM Address Command (02h)
EEPROM Address Pointer
Write To EEPROM Timing
PRG S 1 0 1 0 1 0 1 0 P S 0 0 0 1 0 0 0 0 P S D0 D1 D2 D3 D4 D5 D6 D7 P EEPROM Data (8 LSBs) For EEPROM Address + 0 S D8 D9
D10 D11 D12 D13 D14 D15
No Communication Allowed to EEPROM P EEPROM Write Cycle (5.6ms, typ) S
Initialization Byte (55h)
EEPROM Write Command (08h)
EEPROM Data (8 MSBs) For EEPROM Address + 1
Read From EEPROM Timing
PRG S 1 0 1 0 1 0 1 0 P S 0 0 0 0 0 1 0 0 P One- Byte Period Delay Allows for Bus Direction Change Plus 600s for EEPROM Access Initialization Byte (55h) EEPROM Write Command (20 h)
Driven by PGA309 S D0 D1 D2 D3 D4 D5 D6 D7 P EEPROM Data (8 LSBs) For EEPROM Address + 0 S D8 D9
D10 D11 D12 D13 D14 D15
P
EEPROM Data (8 MSBs) For EEPROM Address + 1
Wire Protocol NOTES: S = START Condition of One- P = STOP Condition of One- Wire Protocol Unless otherwise noted, all transactions are driven by the controller.
Figure 48. One-Wire (PRG) Access to PGA309 and External EEPROM Timing Additional data transfer occurs after the command byte. The number of bytes and direction of data transfer depends on the command byte. For the Set Register Address Pointer command, one additional byte is required to be transmitted by the controller. This is used to select the PGA309 internal register for the next Write Register or Read Register command. For the Write Register command, two additional bytes are required to be transmitted by the controller. These two bytes, transmitted least significant byte first, are stored in the PGA309 internal register pointed to by the register address pointer. The addressed register will be updated with all 16 bits simultaneously at the completion of the transfer of the second byte. For the Read Register command, two additional bytes are transmitted by the PGA309. The PGA309 waits for eight bit periods after the completion of the command byte before beginning to transmit. This allows time for the controller to ensure that the PGA309 will be able to control the One-Wire interface. The first byte transmitted is the least significant byte of the register and the second byte is the most significant byte of the register. For a One-Wire PGA309 register write, the transactions may be repeated immediately one after the other, as shown in Figure 49. For a One-Wire PGA309 register read, the transactions may be repeated after the data has been received from the PGA309, also shown in Figure 49.
Send Initialization Byte
Set Register Address Send Initialization Byte
Send Register Read Command Wait for PGA309 to Send Start (~1 Byte Period)
Set Register Address Send Register Write Command Send Register Data to PGA309 One- Wire Register Write Continuous Sequence
Receive Register Data from PGA309 One- Wire Register Read Continuous Sequence
Figure 49. One-Wire Access to PGA309 Registers
56
PGA309
www.ti.com SBOS292 - DECEMBER 2003
For the Set EEPROM Address Pointer command, two additional bytes are required to be transmitted by the controller. These are used for the EEPROM address for the next Write EEPROM or Read EEPROM command. For the Write EEPROM command, two additional bytes are required to be transmitted by the controller. These two bytes are written to the EEPROM and stored at the address contained in the EEPROM address pointer. The first byte (least significant byte) is written to the address in the EEPROM address pointer. The second byte (most significant byte) is written to the address in the EEPROM address pointer plus one. To avoid any confusion, it is required that the EEPROM address pointer always be set to a value that is even. The first byte is written to the even address and the second byte is written to the next consecutive odd address. The controller is responsible for ensuring that the EEPROM device has enough time to successfully complete the write operation before additional EEPROM communication occurs. For a typical EEPROM, this will be about 5.6ms (0.6ms for the PGA309 to write a 16-bit byte into the EEPROM and 5ms for the EEPROM nonvolatile internal write cycle). For the Read EEPROM command, two additional bytes are transmitted by the PGA309. The PGA309 waits for eight bit periods after the completion of the command byte to allow time for data direction change. The PGA309 also waits for a read communication from the EEPROM device to occur. This will typically be approximately 600s of additional delay. The first byte transmitted is the least significant byte (from address) and the second byte transmitted is the most significant byte (from address + 1). For continuous One-Wire PGA309 EEPROM writes, the controller must insert a typical 5.6ms delay between transactions, as shown in Figure 50. For continuous One-Wire PGA309 EEPROM reads, the transactions may be repeated after the data has been received from the PGA309, as shown in Figure 50. If there is an invalid communication transaction or disconnect with the EEPROM, a One-Wire EEPROM read will be all 1s.
One-Wire Interface Timeout To allow for resynchronization of the One-Wire interface, and if synchronization between the controller and the PGA309 be lost for any reason, a timeout mechanism is implemented. The timeout period is set to approximately 25ms to 35ms. If the timeout period expires between the initialization byte and the command byte, between the command byte and any data byte, or between any data bytes, the PGA309 will reset the One-Wire interface circuitry such that it will be expecting an initialization byte. Every time that a byte is transmitted on the One-Wire interface, this timeout period is restarted.
Send Initialization Byte
Send Initialization Byte
Set EEPROM Address
Set EEPROM Address
Send EEPROM Write C ommand Send Data to EEPRO M
Send EEPROM Read Command
Wait for PGA309 to Send Start (~1 Byte Period)
Wait EEPROM Write Cycle (5.6ms, typ) One- Wire EEPROM Write Continuous Sequence
R eceive Data from EEPRO M One- ire W EEPROM Read Continuous Sequence
Figure 50. One-Wire Access to External EEPROM One-Wire Interface Timing Considerations Figure 51 illustrates the key timing and jitter considerations for the One-Wire interface and Table 29 contains the specifications for ensured, reliable operation. Although the One-Wire baud rate can change from transaction to transaction, within a transaction it must remain within 1% of its initialization byte value.
57
PGA309
www.ti.com SBOS292 - DECEMBER 2003
BaudTYP Jitter+ tR tF Jitter-
Figure 51. One-Wire Timing Diagram
PARAMETER Baud Rise Time, tR Fall Time, tF Jitter(1) MIN 4.8K TYP MAX 38.4K 0.5 0.5 1 UNITS Bits/s %Baud %Baud %Baud
(1) Transmit jitter from controller to PGA309. Standard UART interfaces will accept data sent from the PGA309 during One-Wire transactions.
Table 29. One-Wire Timing Diagram Definitions Two-Wire Access to External EEPROM The read and write timing for the PGA309 interface to the external EEPROM when the PGA309 receives commands through the One-Wire interface (PRG pin) is shown in Figure 52. If direct Two-Wire access is made to the external EEPROM, all manufacturer reading and writing modes are allowed. Note that the PGA309 One-Wire access to the external EEPROM through the PGA309 Two-Wire interface supports full 10-bit EEPROM addressing mode. This allows the user
to store other configuration information in a larger than needed external EEPROM, since a 1K EEPROM is the largest needed for PGA309 configuration register and Lookup Table coefficients. In addition, please note that the PGA309 SCL and SDA pins have light internal pull-up current sources to VSD (85A typical on each pin). This is more than adequate for most applications that involve placing only the external EEPROM close to the PGA309 on the same printed circuit board (PCB). Other applications that add load and capacitance to the SDA and SCL lines may need additional external pull-up resistors to VSD to ensure the rise timing requirements are met at all times. At the end of a EEPROM write cycle, there is a typical 5ms EEPROM write cycle during which the data is stored in a nonvolatile fashion internally to the EEPROM. During this time, if Two-Wire direct access is attempted, there will be no acknowledge from the EEPROM. If communicating to the external EEPROM through the PGA309 One-Wire interface, this EEPROM write cycle time is a "No Communication Allowed" time period.
EEPROM Write Timing: Two- Wire Through PGA309 One- Wire EEPROM Write Timing: Two- Wire Direct
Slave ID SDA 1 0 1 0 P10 P9 P8 Block Address Control Byte R/W 0 A E P7 P6 P5 P4 P3 P2 Word Address P1 P0 A A E D7 D6 D5 D4 D3 D2 D1 D0 E EEPROM Data (8 LSBs) for EEPROM Address + 0
D15 D14 D13 D12 D11 D10 D9 D8
No Communication Allowed to EEPROM A E
P S
S
EEPROM Data (8 MSBs) for EEPROM Address + 1
EEPROM Write Cycle (5ms, typ)
EEPROM Read Timing: Two- Wire Through PGA309 One- Wire EEPROM Random Read Timing: Two- Wire Direct
Slave ID R/W Slave ID A E P7 P6 P5 P4 P3 P2 P1 P0 Word Address Block Address Control Byte Block Address Control Byte A E R/W A E D7 D6 D5 D4 D3 D2 D1 D0 EEPROM Data (8 LSBs) for EEPROM Address + 0 A P
D15 D14 D13 D12 D11 D10 D9 D8
SDA
S
1
01
0 P10 P9 P8
0
S
1 0 1 0 P10 P9 P8 1
A P
P
EEPROM Data (8 MSBs) for EEPROM Address + 1
NOTES: S = START Condition of Two-Wire Protocol P = STOP Condition of Two- Wire Protocol A = Acknowledge from PGA309 P A = Not Acknowledge from PGA309 P A = Acknowledge from EEPROM E
Figure 52. Two-Wire Access to External EEPROM Timing
58
PGA309
www.ti.com SBOS292 - DECEMBER 2003
One-Wire Interface Initiated Two-Wire EEPROM Transactions The Write EEPROM and Read EEPROM commands initiate a communication transaction on the Two-Wire bus between the PGA309 and the EEPROM device (see Figure 52). The Write EEPROM command causes the PGA309 to generate a Two-Wire start condition and send a Two-Wire slave address byte to the EEPROM device with the four MSBs set to `1010' and the three LSBs set to bits 10-8 of the EEPROM address pointer. The R/W bit is set to `0' to indicate a write instruction. If the PGA309 receives an acknowledge from the EEPROM device, it then sends a byte with eight LSBs of the EEPROM address pointer. If the PGA309 receives an acknowledge from this byte, the PGA309 sends the least significant byte of the data to the EEPROM. Upon successful receipt of an acknowledge to this byte, the PGA309 transmits the most significant byte. After the acknowledge bit of this byte, the PGA309 generates a Two-Wire stop condition to terminate data transfer to the EEPROM. The Read EEPROM command causes the PGA309 to generate a Two-Wire start condition and send a Two-Wire slave address byte to the EEPROM with the four MSBs set to `1010', the three LSBs set to bits 10-8 of the EEPROM Address Pointer, and the R/W bit set to `0' to indicate a write instruction. If the PGA309 receives an acknowledge from the EEPROM device, it will then send a byte with the eight LSBs of the EEPROM address pointer. If the PGA309 receives an acknowledge from this byte, the PGA309 generates another Two-Wire START
condition, send another slave address byte but this time with the R/W bit set to `1' to indicate a read instruction. If the PGA309 receives an acknowledge, it continues to clock the SCL line to receive the first byte from the EEPROM, acknowledge this byte, receive the second byte, not acknowledge the second byte to terminate data transfer, and then generate a Two-Wire STOP condition. PGA309 Stand-Alone Mode and Two-Wire Transactions In Stand-Alone mode (see Operating Modes section), the PGA309 accesses the external EEPROM in a different fashion than that presented for the One-Wire Interface Initiated Two-Wire Transactions. If all other POR conditions have been met to allow a PGA309 to allow access to a properly programmed external EEPROM, the PGA309 will first access the first part of the external EEPROM (configuration register data) as shown in Figure 53. If the Checksum1 is correct and the PGA309 is triggered to read the second part of the EEPROM, it will proceed as shown in Figure 54. If the One-Wire disable bit, OWD, bit 15, in Register 4 is set to `1' then after initial POR and following a valid Checksum2, the One-Wire interface is disabled and the PRG pin becomes high impedance and One-Wire communication cannot take place unless power is cycled. This is part of the provisions to allow for direct connection of the PRG pin to VOUT.
EEPROM Read Timing: Two- Wire by PGA309 Master First Part of EEPROM: Configuration Registers
Slave ID R/W A E A E Slave ID R/W A A E D7 D6 D5 D4 D3 D2 D1 D0 P Programmed Flag Value (LSBs) Block Address Control Byte A P
SDA
S
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
S
1
01
0
0
0
0
1
D15 D14 D13 D12 D11 D10
D9
D8
Block Address Control Byte
Word Address
Programmed Flag Value (MSBs)
Register 3, 4, 5, 6 Configuration Data Wire Protocol NOTES: S = START Condition of Two- P = STOP Condition of Two- Wire Protocol A = Acknowledge from PGA309 P A = Not Acknowledge from PGA309 P A = Acknowledge from EEPROM E D7 D6 D5 D4 D3 D2 D1 D0 Checksum1 (LSBs) Address 00Eh A P
D15 D14 D13 D12 D11 D10 D9 D8
A P
P
Checksum1 (MSBs) Address 00Fh
Figure 53. First Part of External EEPROM Timing for Stand-Alone Mode
59
PGA309
www.ti.com SBOS292 - DECEMBER 2003
EEPROM Read Timing: Two- Wire by PGA309 Master Second Part of EEPROM: Lookup Table Coefficients
Slave ID R/W A E A E Slave ID R/W A A 1 E D7 D6 D5 D4 D3 D2 D1 D0 P Temperature Index Value T0 (LSBs) Block Address Control Byte Lookup Table Coefficients Wire Protocol NOTES: S = START Condition of Two- P = STOP Condition of Two- Wire Protocol A = Acknowledge from PGA309 P A = Not Acknowledge from PGA309 P A = Acknowledge from EEPROM E D7 D6 D5 D4 D3 D2 D1 D0 Checksum2 (LSBs) A P
D15 D14 D13 D12 D11 D10 D9 D8
SDA
S
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
S
1
01
0
0
0
0
D15 D14 D13 D12 D11 D10
D9
D8
A P
Block Address Control Byte
Word Address
Temperature Index Value T0 (MSBs)
A P
P
Checksum2 (MSBs)
Figure 54. Second Part of External EEPROM Timing for Stand-Alone Mode PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations Whenever the PGA309 is called upon to communicate to the external EEPROM, the PGA309 needs to become the master on the Two-Wire interface bus. In order to do this in a reliable and orderly fashion, the PGA309 contains several monitors and algorithms to check for bus availability, prevent bus contention in case other devices are connected in parallel with the External EEPROM, and fault diagnostics to attempt to free a stuck bus. If the PGA309 is ever addressed on its Two-Wire or One-Wire interface, with it providing a successful acknowledge, it will cease all transactions as a master on the Two-Wire bus and give up control for one second. Each time the PGA309 is addressed on the Two-Wire bus, the one second timeout is reset (see Figure 55). Figure 56 details the algorithms used by the PGA309 when it wants to become master on the Two-Wire bus. A 25ms timer is started. Now SCL is monitored for being low. If SCL is not low, the PGA309 checks to see if communication on the Two-Wire bus is between a START and a STOP. If the bus communication is between a START and a STOP, the PGA309 waits for the 25ms timer to time out, and then checks if SDA is low. If SDA is not low, the PGA309 has an opportunity to become bus master (SCL = SDA = `1') and takes it. During the 25ms interval, if there is any SCL activity, the 25ms timer will restart. If SCL remains low for the entire 25ms timer countdown, the PGA309 waits 25ms before starting the 25ms timer again to begin the check of the bus for an idle state (SDA = SCL = `1'). If SDA is low after the 25ms timer counts down, the PGA309 interprets this as a stuck-bus condition. The PGA309 attempts to free the stuck bus by sending up to ten clocks down SCL to free up SDA. If it is successful
60
in causing SDA to go high, the PGA309 sends a START and then STOP sequence to ensure whichever device was causing the stuck bus is completely reset. Now the bus should be in an idle state (SDA = SCL = `1') and the PGA309 can become the master on the bus.
POR
Wait 25ms
PGA309 is Master on Two- Wire Bus
PGA309 Addressed? (One- Wire or Two- Wire) Yes Release Bus and Stop as Master
No
Wait 1 Second
Figure 55. Two-Wire Bus Relinquish by PGA309 in Master Mode If the PGA309 is communicating on the bus as a master and it sees contention, the PGA309 will release the bus and retry in 25ms. Contention is defined as the PGA309 wanting SCL high and SCL is low, or wanting SDA high and SDA is low.
PGA309
www.ti.com SBOS292 - DECEMBER 2003
PGA309 wants to be Master
Start 25ms Timer
SCL = 0 ? No
Yes
Timer > 25ms ? Yes
No
Wait 25ms
Between Start and Stop ? No
Yes
Timer > 25ms ? Yes
No
SDA = 0?
Yes
Timer > 25ms ? Yes
No
No
No PGA309 Becomes Master Yes Bus Free? SDA = SCL = 1 ?
SDA = 1 ? No
Send START Send STOP
Yes
10 SCL Clocks Sent ? No
Yes
Send SCL Clock
Figure 56. Two-Wire Bus Master Algorithm
61
PGA309
www.ti.com SBOS292 - DECEMBER 2003
One-Wire Operation with PRG Connected to VOUT In some sensor applications, it is desired to provide the end-user of the sensor module with three pins, VS, GND, and Sensor Out. It is also desired in these applications to digitally calibrate the sensor module after its final assembly of sensor and electronics. The PGA309 has a mode that allows the One-Wire interface pin (PRG) to be tied directly to the PGA309 output pin (VOUT), as shown in Figure 57. For the PGA309 + sensor calibration, it is necessary to configure and reconfigure internal registers on the PGA309 and then measure the analog voltage on VOUT as a result of these register value settings. To do this while VOUT is tied to PRG requires the ability to enable and disable VOUT. This allows a multiplexing operation between PRG using the connection as a bidirectional digital interface and VOUT driving the connection as a
conditioned sensor output voltage. In addition, it is convenient to configure the Temp ADC for Single Start Convert mode and delay the start of the Temp ADC until after VOUT is enabled and internal circuitry has had a chance to settle to accurate final values. This is especially important in applications that use the linearization circuitry, tie the sensor to VEXC, and measure temperature external to the PGA309 (i.e., temperature sense series resistor in the upper or lower excitation leg of the bridge sensor). Register 7 (Output Enable Counter Control Register) contains the control bits for setting both the amount of time VOUT is active on the common connection and also the delay from VOUT enabled to the start of a Temp ADC conversion. These individual bits are defined in Table 30 and Table 31.
+5V
Three-Wire Sensor Module +5V VSD VSA REFIN/REFOUT Sensor Out GND RISO 100 CL 10nF
Power Supply +- VCC 1- Wire GND SDA SCL PGA309 EVM Interface Board RS232
Easy-to-Use Calibration
+5V SDA Two-Wire EEPROM PRG SCL VOUT VEXC
PC
PGA309
VIN2
VFB
RFB 100
CF 150pF
Bridge Sensor
VIN1
VSJ
TEMPIN
Test
GNDA
GNDD
Figure 57. One-Wire Operation with PRG Tied to VOUT
62
PGA309
www.ti.com SBOS292 - DECEMBER 2003 DLY 3 [11] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DLY 2 [10] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DLY 1 [9] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DLY 0 [8] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DECIMAL EQUIVALENT (INITIAL COUNTER VALUE) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TEMP ADC DELAY (ms) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
enabled until this initial Output Enable Counter value is decremented to 0 by 10ms increments. VOUT is then disabled and a one second timeout begun waiting for bus activity on either digital interface (PRG pin for three-wire sensor application). As long as there is activity on the PRG pin, the one second timeout will be continually reset. After one second of no bus activity, the PGA309 stops and the state machine will try to read the EEPROM. It is important to store invalid data in the programmed flag values of the EEPROM for this calibration process, to prevent it from being read, which could change the register settings in the PGA309. This will also force the one second timeout to be reset and allow as long as needed for communication to start and stop on PRG. Once all registers in the PGA309 have been set to their desired values, another write to Register 7 will start the process all over again so a new analog value of VOUT can be measured. The second part of the output enable/disable state machine is the Temp ADC delay. During calibration, it will be desired to read the Temp ADC conversion result at different absolute calibration temperatures. These readings combined with measured VOUT at these respective temperatures are used to calculate the final temperature coefficients to be stored in the Lookup Table part of the external EEPROM. To use this function, the Temp ADC must be set to Single Start Convert mode (CEN = 0, Register 6 [10]). After a write to Register 7, the Temp ADC delay counter is loaded with the DLY3:DLY0 value (decimal equivalent x 10ms = initial Temp ADC delay counter value). This initial Temp ADC delay counter value is decremented to 0 by 10ms increments. When it reaches 0, a single Temp ADC conversion is triggered. No additional write to Register 6 [12] (the ADCS bit) is needed to initiate the conversion. Upon completion of the conversion, this branch of the state machine returns to waiting for the next valid Register 7 write. The output enable/disable state machine allows three-wire sensor applications to measure temperature through the PGA309, against the calibration standard, for the PGA309 + sensor combination. It also allows PGA309 + sensor characteristics over pressure and temperature to be measured through the PGA309. These real-world results allow for accurate calculation of temperature coefficients for the Lookup Table and therefore, accurate PGA309 + sensor digital calibration on a module-by-module basis. The values of the Fault Monitor Alarm bits are latched immediately before the output is disabled to allow their values to be read through the One-Wire interface during factory calibration.
NOTE: Temp ADC delay = intial counter value x 10ms.
Table 30. Temp ADC--Delay After VOUT Enable (Register 7)
DIGITAL INPUT (BINARY) OEN700OEN0 [7000] 0000 0000 0010 0000 0100 0000 0110 0000 1000 0000 1010 0000 1100 0000 1110 0000 1111 1111 DECIMAL EQUIVALENT (INITIAL COUNTER VALUE) 0 32 64 96 128 160 192 224 255
VOUT ENABLE TIMEOUT (ms) 0 (VOUT Disabled) 320 640 960 1280 1600 1920 2240 2550
NOTE: VOUT enable timeout = inital counter value x 10ms.
Table 31.
Output Enable Counter for One-Wire Interface/VOUT Multiplexed Mode (Register 7)
Figure 58 details the output enable/disable state machine. Upon initial POR, there is 25ms for communication through either digital interface to prevent the PGA309 from going through its POR sequence and reaching Stand-Alone mode. At any time the PGA309 is powered and either digital interface (One-Wire or Two-Wire) can write to Register 7, the output enable/disable state machine can be forced to run. Writing a non-zero value to OEN7:OEN0 will cause VOUT to be immediately enabled and the Output Enable Counter to be loaded with the OEN7:OEN0 value (decimal equivalent x 10ms = initial Output Enable Counter value). VOUT remains
63
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Once the final values are to be programmed into the EEPROM, it is desirable to have the One-Wire Interface disabled in three-wire sensor applications. This prevents VOUT changes in the final end-use from being read back into the PGA309 through the One-Wire interface (PRG pin) and potentially misinterpreted as bus activity, which could then cause VOUT to become
disabled. To disable the One-Wire Interface, set the OWD bit to `1' during the final EEPROM program write. The OWD (One-Wire Disable) bit is located in Register 4 [15]. After this final programming, all is not lost as any power-up sequence will allow the One-Wire Interface (PRG pin) control if communication is initiated within 25ms of the application of power to the PGA309.
Wait for Register 7 Write One- Wire or Two- Wire
No
Valid Write to Register 7 ? Yes
Load Temp ADC Delay Counter (DLY3:DLY0)
Temp ADC Conversion Complete
VOUT = Disable
Yes
OEN7:OEN0
all 0's ? No VOUT = Enable
Wait 10ms
Start Single Temp ADC Conversion No Yes Yes No PGA309 Stand- Alone Mode(2)
Decrement Temp ADC Delay Counter
Temp ADC Delay Count =0?
CEN = 0 ?
Load Output Enable Counter (OEN7:OEN0) No Wait 10ms
Read EEPROM
Valid EEPROM Flag Values?(1)
No Decrement Output Enable Counter
Output Enable Counter = 0 ?
Yes Yes
V O UT = Disable
Yes No 1 Second Timeout Expired? No
Sample Alarm Bits
Start 1 Second Timeout
Bus Activity? One- Wire or Two- Wire
NOTES: (1) For calibration using PRG tied to VOUT, set EEPROM programmed flag values to invalid values to prevent PGA309 registers from having their values changed by EEPROM register configuration and lookup table data. (2) In PGA309 Stand- Alone mode, if OWD (Register 4 [15]) is set to '1' in the first part of EEPROM (configuration part), then the One- Wire interface is disabled and the only way to communicate over the One- Wire interface is to cycle power on the PGA309 and begin communication over the One- Wire interface within 25ms of power on.
Figure 58. Output Enable/Disable State Machine
64
PGA309
www.ti.com SBOS292 - DECEMBER 2003
APPLICATION BACKGROUND
A typical bridge pressure sensor is shown in Figure 59. For a given bridge excitation voltage (VEXC), the output voltage of the bridge (VINP - VINN) is a voltage proportional to the pressure applied to the sensor. Span is the scale factor for VINP - VINN at full-scale pressure input relative to the bridge excitation (VBR+ - VBR-). Span is also called FSO (Full-Scale Output), FSS (Full-Scale Sensitivity), Sensitivity, or Gain. For example, with a bridge excitation voltage of 5V, a 2mV/V FSS implies that the bridge output will be 10mV at full-scale pressure. Offset, also known as Zero, is the output of the bridge (VINP - VINN) with zero pressure applied. Often a bridge sensor's Zero may be equal to or greater than its FSS for a given excitation voltage. Figure 60 graphically illustrates the definition of Span and Offset.
An ideal sensor would have span and offset curves over temperature, as shown in Figure 3. Real-world sensors have span and offset changes that change over temperature. Both span and offset have variations at +25C, linear changes with temperature, and nonlinear changes with temperature. Figure 4 and Figure 5 illustrate span and offset changes over temperature for a bridge sensor with second-order nonlinearities. TC1 coefficients represent a linear change with temperature, and TC2 a second-order change with temperature. Many bridge sensors have a nonlinear output with applied pressure. Figure 64 shows the non-ideal curves for both a positive and negative nonlinear bridge sensor output with applied pressure. The PGA309 provides calibration over temperature for both span and offset and has dedicated linearization circuitry to linearize many types of bridge sensors whose outputs are not linear with applied pressure.
0.08 VBR+ 2k RBRG 2k 2k 2k VEXC VINP 2k VINN VBR- 0 -0.02 -40 Temperature (_ C) RBRG 2k VEXC 0.04
0.06 Span
0.02 Offset
125
Figure 59. Typical Bridge Sensor
Figure 61. Ideal Span and Offset vs Temperature
Span Error (% of Span at Room Temp)
0.06 0.05 (VINP - VINN)/VEXC 0.04 0.03 Span 0.02 0.01 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Pressure/PressureFULL-SCALE 0.8 0.9 1.0 Offset
20 15 10 5 0 -5 -10 -15 -20 -25 Span at 25_C = 2%VEXC SpanTC1 = -0.2%Span/_ C SpanTC2 = -3 x 10-6Span/_C2 5 20 35 50 65 Temperature (_C) 80 95 110 125
-30 -40 -25 -10
Figure 60. Example of Span and Offset
Figure 62. Effect of Nonlinearity on Bridge Sensor Span Over Temperature
65
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Offset Error (% of Span at Room Temp)
30 25 20 15 10 5 0 -5 -10 -15 -20 -40 -25 -10 5 20 35 50 65 Temperature (_C) 80 95 110 125 Offset at 25_C = 2%VEXC OffsetTC1 = 0.2%Span/_C OffsetTC2 = -4.4 x 10-6Span/_C2
10 9 8 Bridge Output (mV) 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Normalized Stimulus (PIN/PMAX) 0.9 1.0 Negative Nonlinearity BV = -0.025 (-2.5% FSR) Positive Nonlinearity BV = +0.025 (+2.5% FSR)
Figure 63. Effect of Nonlinearity on Bridge Sensor Offset Over Temperature
Figure 64. Non-Ideal Curves for Both a Positive and Negative Nonlinear Bridge Sensor Output with Applied Pressure Absolute Scale Absolute Scale conditions the output range to be scaled as a percentage of a reference voltage, VREF. For example, the absolute-scaled output of a bridge sensor can be set to the range of 10% to 90% of VREF. Figure 65 illustrates such a case.
SYSTEM SCALING OPTIONS FOR BRIDGE SENSORS There are two system scaling options for bridge sensor outputs: Absolute Scale and Ratiometric Scale.
+3V to +5V
2.25k 0psi 1V DIFF = 0V VBR+
VREF
2.5V Reference
2k
2k
Instrumentation Amplifier R
VOS = 0.25V R 250
2k
2k
VDIFF VBR-
G = X40 R VOUT
R
1 VOUT = 0.25V, 10% VREF 2 VOUT = 2.25V, 90% VREF
2.040k
1.960k 1.275V 2.040k 1.225V 100psi 2 FSS = 20mV/V VDIFF = 50mV
1.960k
Figure 65. Absolute Scaling Conditions
66
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Ratiometric Scale Ratiometric Scale conditions the output range to be scaled as a percentage of the supply voltage. For example, the ratiometric-scaled output of a bridge sensor can be set to the range of 10% to 90% of VS.
Figure 66 illustrates such a case. Figure 67 shows that as the supply voltage, VS, is lowered from +5V to +3V the range for VOUT of 10% to 90% of VS remains the same. The PGA309 accommodates both Absolute and Ratiometric scaling of bridge sensors.
+5V +5V 0 psi 1V DIFF = 0V 2.5V 4.5k Instrumentation Amplifier R 2k 2k VDIFF 2.5V R +5V 1 VOUT = 0.5V, 10% VS 2 VOUT = 4.5V, 90% VS 2.040k 1.960k 2.550V 2.040k 2.450V 100 psi 2 FSS = 20mV/V VDIFF = 100mV G = X40 R VOUT VOS = 0.1VS VOS = 0.5V R 500
2k
2k
1.960k
Figure 66. Ratiometric Configuration, 5V
+3V +3V 0 psi 1V DIFF = 0V 1.5V 4.5k Instrumentation Amplifier R R 2k 2k VDIFF 1.5V R +3V 1 VOUT = 0.3V, 10% VS 2 VOUT = 2.7V, 90% VS 2.040k 1.960k 1.530V 2.040k 1.470V 100 psi 2 FSS = 20mV/V VDIFF = 60mV G = X40 R VOUT VOS = 0.1VS VOS = 0.3V 500
2k
2k
1.960k
Figure 67. Ratiometric Configuration, 3V
67
PGA309
www.ti.com SBOS292 - DECEMBER 2003
TRIMMING REAL WORLD BRIDGE SENSORS FOR LINEARITY Traditional methods for trimming nonlinear, real-world bridge sensors to a linear, useful function require additional resistors to be added around the base bridge sensor, as shown in Figure 68. This approach often requires special prepackaged fixtures and special laser trim or manual trim resistors. The trims are interactive with each other, which requires multiple test/trim/test/trim passes and this only allows for a finite number of trims and range for a particular bridge sensor.
The PGA309 provides a modern digital trim approach for bridge sensors, as shown in Figure 69. This technique allows for post-package trim of both the bridge sensor and its signal conditioning electronics. The digital trimming is simplified through the use of a computer interface and spreadsheet analysis computation tools. A near infinite number of trim cycles can be performed with finer resolution, wider range, and less interaction between trimmed parameters than the traditional trim. Packaging shifts are eliminated.
VBR+ Offset Drift Trim Sensitivity Drift Trim Zero Trim1 Zero Trim2 VBR- VINP
VINN
Figure 68. Typical Trim Configuration
VS
PGA309 Reference
Nonlinear Bridge Transducer
VEXC
Linearization Ckt
Linearization DAC Fault Monitor Over/Under- Scale Limiter
Auto-Zero PGIA
Linear VOUT
Digital Calibration Internal Temperature Lookup and Interpolation Logic EEPROM (SOT23-5) 1K Bit External Temperature Temperature ADC External Temperature
Figure 69. PGA309 Trim Configuration
68
PGA309
www.ti.com SBOS292 - DECEMBER 2003
REGISTER DESCRIPTIONS
PGA309 INTERNAL REGISTER OVERVIEW
ADDRESS POINTER P4 0 0 0 0 0 0 P3 0 0 0 0 0 0 P2 0 0 0 0 1 1 P1 0 0 1 1 0 0 P0 0 1 0 1 0 1 REGISTER DESCRIPTION Register 0--Temp ADC Output Register 1--Fine Offset Adjust (Zero DAC) Register 2--Fine Gain Adjust (Gain DAC) Register 3--Reference Control and Linearization Register Register 4--Front End PGA Coarse Offset Adjust and Gain Select; Output Amplifier Gain Select Register 5--PGA Configuration and Over/Under Scale Limit TYPE(1) R R/W R/W R/W R/W R/W REGISTER CONTROLS Temp ADC Output Data Fine Offset Adjust (Zero DAC) Setting Fine Gain Adjust (Gain DAC) Setting Reference Configuration Settings; VEXC Enable; Linearization Setting Front End PGA Coarse Offset Setting; PGA Gain Select; Output Amplifier Gain Select; One-Wire Disable Over/Under Scale Limits, Polarities, Enable; Fault Comparator Select Temp ADC Conversion Speed, Ref Select; Int/Ext Temp Mode Select; Ext Temp PGA Configuration; TEMPIN Current Source Enable Temp ADC Delay Setting; One-Wire Interface Output Enable Setting Fault Monitor Comparator Outputs
0 0 0
0 0 1
1 1 0
1 1 0
0 1 0
Register 6--Temp ADC Control Register Register 7--Output Enable Counter Control Register 8--Alarm Status
R/W R/W R
(1) Type: R = Read-only, R/W = Read/Write
Table 32. PGA309 Internal Register Overview
69
PGA309
www.ti.com SBOS292 - DECEMBER 2003
INTERNAL REGISTER MAP Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
BIT # BIT NAME POR VALUE D15 AD15 0 D14 AD14 0 D13 AD13 0 D12 AD12 0 D11 AD11 0 D10 AD10 0 D9 AD9 0 D8 AD8 0 D7 AD7 0 D6 AD6 0 D5 AD5 0 D4 AD4 0 D3 AD3 0 D2 AD2 0 D1 AD1 0 D0 AD0 0
Bit Descriptions: AD[15:0] Temp ADC Output
Internal Temperature Mode: 12-bit + sign extended, right justified, Two's Complement data format External Temperature Mode: 15-bit + sign extended, right-justified, Two's Complement data format
Temp ADC Internal REF
On- Chip Diodes
ADC
16- Digital Output: Bit 12- + Sign Extended, Right Justified, Bit Two's Complement Data Format
Resolution/Update Rate Register 6[1,0]
Figure 70.
TEMPERATURE (C) 150 128 127.9375 100 80 75 50 25 0.25 0.0 -0.25 -25 -55
DIGITAL OUTPUT AD15............AD0 (BINARY) 0000 1001 0110 0000 0000 1000 0000 0000 0000 0111 1111 1111 0000 0110 0100 0000 0000 0101 0000 0000 0000 0100 1011 0000 0000 0010 0010 0000 0000 0001 1001 0000 0000 0000 0000 0100 0000 0000 0000 0000 1111 1111 1111 1100 1111 1110 0111 0000 1111 1100 1001 0000
DIGITAL OUTPUT (HEX) 0960 0800 07FF 0640 0500 04B0 0320 0190 0004 0000 FFFC FE70 FC90
Table 33. Internal Temperature Mode--Data Format (12-Bit Resolution). TEN = 1; R1, R0 = `11'
70
PGA309
www.ti.com SBOS292 - DECEMBER 2003
VREF = 2.5V Positive Input VREF = 2.5V 0V +5V TEMPIN Negative Input Temp PGA X1 +2.5V -2.5V ADC 16- Bit Temp ADC +FS Digital Out -FS Digital Out
Figure 71.
DIGITAL OUTPUT AD15............AD0 (BINARY) 0111 1111 1111 1111 0110 0000 0000 0000 0100 0000 0000 0000 0001 1101 0111 0001 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1110 0010 1000 1111 1100 0000 0000 0000 1010 0000 0000 0000 1000 0000 0000 0000
TEMPIN (V) +0.0001 +0.625 +1.25 +1.925 +2.4999 +2.5 +2.50007629 +3.075 +3.75 +4.375 +5
TEMP ADC INPUT (V) +2.49992371 +1.875 +1.25 +0.575 +76.29 0 -76.29 -0.575 -1.25 -1.875 -2.5
TEMP ADC INPUT (RATIO TO FULL SCALE)(1) +0.999969 VREFT +0.75 VREFT +0.5 VREFT +0.23 VREFT +(1/32768) VREFT +0 VREFT -(1/32768) VREFT -0.23 VREFT -0.5 VREFT -0.75 VREFT -1 VREFT
DIGITAL OUTPUT (HEX) 7FFF 6000 4000 1D71 0001 0000 FFFF E28F C000 A000 8000
(1) VREFT can be VSA, VEXC, or VREF.
Table 34. External Signal Mode--Data Format Example (Register 6 = `0000 0100 0011 0011'), 15-Bit + Sign Resolution. REN = 1, RS = 1.
71
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
BIT # BIT NAME POR VALUE D15 ZD15 0 D14 ZD14 1 D13 ZD13 0 D12 ZD12 0 D11 ZD11 0 D10 ZD10 0 D9 ZD9 0 D8 ZD8 0 D7 ZD7 0 D6 ZD6 0 D5 ZD5 0 D4 ZD4 0 D3 ZD3 0 D2 ZD2 0 D1 ZD1 0 D0 ZD0 0
Bit Descriptions: ZD[15:0]: Zero DAC control, 16-bit unsigned data format
DIGITAL INPUT ZD15............ZD0 (BINARY) 0000 0000 0000 0000 0000 0000 0000 0001 0000 0101 0001 1111 0100 0000 0000 0000 1000 0000 0000 0000 1100 0000 0000 0000 1111 1010 1110 0001 1111 1111 1111 1111
DIGITAL INPUT (HEX) 0000 0001 051F 4000 8000 C000 FAE1 FFFF
ZERO DAC OUTPUT (V) 0 0.00007629 0.100021362 1.25 2.5 3.75 4.899978638 4.999923706
ZERO DAC OUTPUT 0 VREF (1/65536) VREF 0.02 VREF(1) 0.25 VREF 0.50 VREF 0.75 VREF 0.98 VREF(1) 0.9999847 VREF
(1) Ensured by design Zero DAC Range of Adjustment (0.02VREF to 0.98VREF)
Table 35. Zero DAC--Data Format Example (VREF = +5V)
Zero DAC Equation:
Decimal # Counts = VZERO DAC / (VREF/65536)
Zero DAC Example:
Want: VZERO DAC = 0.5V Given: VREF = 5V Decimal # Counts = 0.5 / (5/65536) = 6553.6 Use 6554 counts 0x199A 0001 1001 1001 1100
72
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
BIT # BIT NAME POR VALUE D15 GD15 0 D14 GD14 1 D13 GD13 0 D12 GD12 0 D11 GD11 0 D10 GD10 0 D9 GD9 0 D8 GD8 0 D7 GD7 0 D6 GD6 0 D5 GD5 0 D4 GD4 0 D3 GD3 0 D2 GD2 0 D1 GD1 0 D0 GD0 0
Bit Descriptions: GD[15:0]: Gain DAC control, 16-bit unsigned data format
DIGITAL INPUT (HEX) 0000 0001 32F2 4000 6604 9979 CC86 FFFF DIGITAL INPUT ZD15............ZD0 (BINARY) 0000 0000 0000 0000 0000 0000 0000 0001 0011 0010 1111 0010 0100 0000 0000 0000 0101 0101 0000 0100 1001 1001 0111 1001 1100 1100 1000 0110 1111 1111 1111 1111
GAIN ADJUST 0.333333333 0.333343505 0.466003417 0.500000000 0.598999023 0.733001708 0.865997314 1.000000000
Table 36. Gain DAC--Data Format
Gain DAC Equation:
1 LSB = (1.000000000 - 0.333333333) / 65536 = 1.0172526 x 10-5 Decimal # counts = (Desired Gain - 0.333333333) / (1.0172526 x 10-5)
Gain DAC Example:
Want: Fine Gain = 0.68 Decimal # counts = (0.68 - 0.333333333) / (1.0172526 x 10-5) = 34,078.72 Use 34079 counts 0x851F 1000 0101 0001 1111
73
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
BIT # BIT NAME POR VALUE D15 RFB 0 D14 RFB 0 D13 RFB 0 D12 SD 0 D11 EXS 0 D10 EXEN 0 D9 RS 0 D8 REN 0 D7 LD7 0 D6 LD6 0 D5 LD5 0 D4 LD4 0 D3 LD3 0 D2 LD2 0 D1 LD1 0 D0 LD0 0
Bit Descriptions: RFB: SD: EXS: Reserved Factory Bit: Set to zero for proper operation Analog Shutdown Mode for Internal Controlled Power-Up (0 = enabled, 1 = disabled) Linearization Adjust and Excitation Voltage (VEXC) Gain Select (Range1 or Range2)
0 = Range 1 (-0.166VFB < Linearization DAC Range < +0.166VFB, VEXC Gain = 0.83VREF) 1 = Range 2 (-0.124VFB < Linearization DAC Range < +0.124VFB, VEXC Gain = 0.52VREF)
EXEN:
VEXC Enable
1 = Enable VEXC 0 = Disable VEXC
RS:
Internal VREF Select (2.5V or 4.096V)
0 = 4.096V 1 = 2.5V
REN:
Enable/Disable Internal VREF (disable for external VREF--connect external VREF to REFIN/REFOUT pin)
0 = External Reference (disable internal reference) 1 = Internal Reference (enable internal reference)
LD[7:0]: Linearization DAC setting, 7-bit + sign
DIGITAL INPUT (HEX) FF E0 C0 A0 81 00 01 20 40 60 7F DIGITAL INPUT LD7......LD0 (BINARY) 1111 1111 1110 0000 1100 0000 1010 0000 1000 0001 0000 0000 0000 0001 0010 0000 0100 0000 0110 0000 0111 1111
LINEARIZATION ADJUST -0. 164703125 VFB -0.1245 VFB -0.083 VFB -0.0415 VFB -0.001296875 VFB 0 VFB +0.001296875 VFB +0.0415 VFB +0.083 VFB +0.1245 VFB +0.164703125 VFB
Table 37. Linearization DAC--Data Format Example (Range 1: -0.166VFB < Linearization DAC Range < +0.166VFB)
Linearization DAC Equation:
Decimal # counts = |Desired KLIN| / (Full-Scale Ratio/128)
Linearization DAC Example:
Given: (Range 1: -0.166VFB < Linearization DAC Range < +0.166VFB) Want: KLIN Ratio = -0.082 Decimal # counts = 0.082 / (0.166/128) = 63.228 Use 63 counts 0x3F 0011 1111 However, we want -0.082, so we add a `1' in the sign bit (MSB, bit 7) for negative ratio: Final Linearization DAC setting: 1011 1111 0xBF
74
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
BIT # BIT NAME POR VALUE D15 0WD 0 D14 GO2 0 D13 GO1 0 D12 GO0 0 D11 GI3 0 D10 GI2 0 D9 GI1 0 D8 GI0 0 D7 RFB 0 D6 RFB 0 D5 RFB 0 D4 OS4 0 D3 OS3 0 D2 OS2 0 D1 OS1 0 D0 OS0 0
Bit Descriptions: OWD: One-Wire Disable (only valid while VOUT is enabled, for use when PRG is connected to VOUT)
1 = Disable 0 = Enable
GO[2:0]: Output Amplifier Gain Select, 1-of-7 plus internal feedback disable GI[3:0]: Front-End PGA Gain Select, 1-of-8, and Input Mux Control
GI3 = Input Mux Control GI[2:0] = Gain Select
RFB:
Reserved Factory Bit: Set to zero for proper operation
1LSB = VREF/1250
GO2 [14] 0 0 0 0 1 1 1 1 GO1 [13] 0 0 1 1 0 0 1 1 GO0 [12] 0 1 0 1 0 1 0 1 OUTPUT AMPLIFIER GAIN 2 2.4 3 3.6 4.5 6 9 Disable Internal Feedback
OS[4:0]: Coarse Offset Adjust on Front-End PGA, 4-bit + sign
Table 38. Output Amplifier--Gain Select
GI3 MUX CNTL [11] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GI2 GAIN SEL2 [10] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 GI1 GAIN SEL1 [9] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GI0 GAIN SEL0 [8] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FRONT-END PGA GAIN 4 8 16 23.27 32 42.67 64 128 -4 -8 -16 -23.27 -32 -42.67 -64 -128
INPUT MUX STATE(1) VIN1 = VINP, VIN2 = VINN VIN1 = VINP, VIN2 = VINN VIN1 = VINP, VIN2 = VINN VIN1 = VINP, VIN2 = VINN VIN1 = VINP, VIN2 = VINN VIN1 = VINP, VIN2 = VINN VIN1 = VINP, VIN2 = VINN VIN1 = VINP, VIN2 = VINN VIN1 = VINN, VIN2 = VINP VIN1 = VINN, VIN2 = VINP VIN1 = VINN, VIN2 = VINP VIN1 = VINN, VIN2 = VINP VIN1 = VINN, VIN2 = VINP VIN1 = VINN, VIN2 = VINP VIN1 = VINN, VIN2 = VINP VIN1 = VINN, VIN2 = VINP
(1) VIN1 = Pin 4, VIN2 = Pin 5, VINP = positive input to front-end PGA, VINN = negative input to front-end PGA; ee detailed block diagram (Figure 75).
Table 39. Front End PGA--Gain Select
75
PGA309
www.ti.com SBOS292 - DECEMBER 2003 OS4 [4] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OS3 [3] 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OS2 [2] 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OS1 [1] 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OS0 [0] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 COARSE OFFSET (mV) -58.3333 -54.1666 -50 -45.8333 -41.6666 -37.5 -33.3333 -29.1666 -29.1666 -25.0 -20.8333 -16.6666 -12.5 -8.3333 -4.1666 0 +4.166 +8.3333 +12.5 +16.6666 +20.8333 +25.0 +29.1666 +29.1666 +33.3333 +37.5 +41.6666 +45.8333 +50 +54.1666 +58.3333
COARSE OFFSET -14(VREF/1200) -13 (VREF/1200) -12 (VREF/1200) -11 (VREF/1200) -10 (VREF/1200) -9 (VREF/1200) -8(VREF/1200) -7 (VREF/1200) -7 (VREF/1200) -6 (VREF/1200) -5 (VREF/1200) -4 (VREF/1200) -3 (VREF/1200) -2 (VREF/1200) -1 (VREF/1200) 0VREF +1 (VREF/1200) +2 (VREF/1200) +3 (VREF/1200) +4 (VREF/1200) +5 (VREF/1200) +6 (VREF/1200) +7 (VREF/1200) +7 (VREF/1200) +8 (VREF/1200) +9 (VREF/1200) +10 (VREF/1200) +11 (VREF/1200) +12 (VREF/1200) +13 (VREF/1200) +14 (VREF/1200)
Table 40. Coarse Offset Adjust on Front-End PGA--Data Format Example (VREF = +5V)
76
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
BIT # BIT NAME POR VALUE D15 RFB 0 D14 RFB 0 D13 CLK_ CFG1 0 D12 CLK_ CFG0 0 D11 EXT EN 0 D10 INT EN 0 D9 EXT POL 0 D8 INT POL 0 D7 RFB 0 D6 OU EN 0 D5 HL2 0 D4 HL1 0 D3 HL0 0 D2 LL2 0 D1 LL1 0 D0 LL0 0
Bit Descriptions: RFB: (Reserved Factory Bit): Set to zero for proper operation
CLK_CFG[1:0]: Clocking scheme for front-end PGA auto-zero and Coarse Offset DAC Chopping EXTEN: Enable External Fault Comparator Group (INP_HI, INP_LO, INN_LO, INN_HI)
1 = Enable External Fault Comparator Group 0 = Disable External Fault Comparator Group
INTEN:
Enable Internal Fault Comparator Group (A2SAT_LO, A2SAT_HI, A1SAT_LO, A1SAT_HI, A3_VCM)
1 = Enable Internal Fault Comparator Group 0 = Disable Internal Fault Comparator Group
EXTPOL:Selects VOUT output polarity when External Fault Comparator Group detects a fault, if EXTEN=1
1 = Force VOUT high when any comparator in the External Fault Comparator Group detects a fault 0 = Force VOUT low when any comparator in the External Fault Comparator Group detects a fault
INTPOL: Selects VOUT output polarity when Internal Fault Comparator Group detects a fault, if INTEN=1
1 = Force VOUT high when any comparator in the Internal Fault Comparator Group detects a fault 0 = Force VOUT low when any comparator in the Internal Fault Comparator Group detects a fault
OUEN:
Over/Under-Scale Limit Enable.
1 = Enable Over/Under-Scale limits 0 = Disable Over/Under-Scale limits
HL[2:0]: Over-Scale Threshold Select LL[2:0]: Under-Scale Threshold Select
CLK_CFG1 [13] 0 0 1 1 CLK_CFG0 [12] 0 1 0 1 PGA FRONT END AUTO-ZERO 7kHz typical 7kHz typical 7kHz typical, Random Clocking 7kHz typical
COARSE ADJUST DAC CHOPPING 3.5kHz typical Off (none) 3.5kHz typical, Random Clocking 3.5kHz typical, Random Clocking
Table 41. Clock Configuration (Front End PGA Auto-Zero and Coarse Adjust DAC Chopping)
HL2 [5] 0 0 0 0 1 1 1 1 HL1 [4] 0 0 1 1 0 0 1 1 HL0 [3] 0 1 0 1 0 1 0 1 OVER-SCALE THRESHOLD (V) 4.854 4.805 4.698 4.580 4.551 3.662 2.764 Reserved
OVER-SCALE THRESHOLD 0.9708 VREF 0.9610 VREF 0.9394 VREF 0.9160 VREF 0.9102 VREF 0.7324 VREF 0.5528 VREF --
Table 42. Over-Scale Threshold Select (VREF = +5V)
77
PGA309
www.ti.com SBOS292 - DECEMBER 2003 LL2 [2] 0 0 0 0 1 1 1 1 LL1 [1] 0 0 1 1 0 0 1 1 LL0 [0] 0 1 0 1 0 1 0 1 UNDER-SCALE THRESHOLD (V) 0.127 0.147 0.176 0.196 0.225 0.254 0.274 0.303
UNDER-SCALE THRESHOLD 0.02540 VREF 0.02930 VREF 0.03516 VREF 0.03906 VREF 0.04492 VREF 0.05078 VREF 0.05468 VREF 0.06054 VREF
Table 43. Under-Scale Threshold Select (VREF = +5V) Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
BIT # BIT NAME POR VALUE D15 RFB 0 D14 RFB 0 D13 ADC 2x 0 D12 ADCS 0 D11 ISEN 0 D10 CEN 0 D9 TEN 0 D8 AREN 0 D7 RV1 0 D6 RV0 0 D5 M1 0 D4 M0 0 D3 G1 0 D2 G0 0 D1 R1 0 D0 R0 0
Bit Descriptions: RFB: Reserved Factory Bit: Set to zero for proper operation
0 = 1X conversion speed (6ms typical, R1, R0 = `00', TEN = `0', AREN = `0') 1 = 2X conversion speed (3ms typical, R1, R0 = `00', TEN = `0', AREN = `0')
ADC2X: Temp ADC runs 2X faster (not for internal Temp Sense Mode)
ADCS:
Start (restart) the Temp ADC (single conversion control if CEN = 0)
0 = No Start/Restart Temp ADC 1 = Start/Restart Temp ADC (each write of a `1' causes single conversion; when conversion is completed ADCS = `0')
ISEN:
TEMPIN Current source (ITEMP) Enable
1 = Enable 7A current source, ITEMP 0 = Disable 7A current source, ITEMP
CEN:
Enable Temp ADC Continuous Conversion Mode
1 = Continuous Conversion mode 0 = Noncontinuous Conversion mode
TEN:
Internal Temperature Mode Enable
1 = Internal Temperature Sensor Mode Enabled 0 = External Signal Mode
For TEN = 1, set the following bits as shown:
ADC2X = 0 ADCS = set as desired CEN = set as desired AREN = 0 RV[1:0] = 00 M[1:0] = 00 G[1:0] = 00 R[1:0] = Set for desired Temp ADC resolution.
AREN:
Temp ADC internal reference enable
1 = Enable Temp ADC internal reference (internal reference is 2.048V typical) 0 = Disable Temp ADC internal reference (use external ADC reference; see RV[1:0])
RV[1:0]: Temp ADC External Reference Select (VSA, VEXC, VREF) M[1:0]:
78
Temp ADC Input Mux Select
PGA309
www.ti.com SBOS292 - DECEMBER 2003
G[1:0]: R[1:0]:
Temp ADC PGA Gain Select (X1, X2, X4, X8) Temp ADC Resolution (Conversion time) Select
RV1 [7] 0 0 1 1 X RV [6] 0 1 0 1 X TEMP ADC REFERENCE (VREFT) VREF VEXC VSA Factory Reserved Temp ADC Internal REF (2.048V)
AREN [8] 0 0 0 0 1
NOTE: X = don't care
Table 44. Temp ADC Reference Select
M1 [5] 0 0 1 1 M0 [4] 0 1 0 1
TEMP ADC PGA +INPUT TEMPIN VEXC VOUT VREF
TEMP ADC PGA -INPUT GNDA TEMPIN GNDA TEMPIN
Table 45. Temp ADC Input Mux Select
G1 [3] 0 0 1 1 G0 [2] 0 1 0 1
TEMP ADC PGA GAIN X1 X2 X4 X8
Table 46. Temp ADC PGA Gain Select
Internal Temperature Mode (Register 6 [9] = `1')
Temp ADC Internal REF
On- Chip Diodes
ADC
16- Digital Output: Bit 12- + Sign Extended, Right Justified, Bit Two's Complement Data Format
Resolution/Update Rate Register 6[1,0]
Figure 72.
79
PGA309
www.ti.com SBOS292 - DECEMBER 2003
External Signal Mode (Register 6 [9], TEN = `0')
VREF Temp ADC Internal REF VREFT = 2.048V VEXC VREF VOUT TEMPIN Temp ADC Input Mux Temp ADC PGA (X1, X2, X4, X8) Register 6[3,2] Register 6[G1,G2]
VEXC
VSA
Temp ADC REF Mux VREFT Temp ADC 16- Digital Output: Bit Two's Complement, Signed Value (13 to 16 significant bits, right justified)
GNDA
Resolution/Update Rate Register 6[1,0] Register 6[R1,R0]
Figure 73.
Temp ADC Input Mux Configuration #1 Register 6[5:4] = '00' (default) Register 6[M1,M0] = '00' (default) Positive Input TEMPIN
Temp ADC Input Mux Configuration #3 Register 6[5:4] = '10' Register 6[M1,M0] = '10' Positive Input VOUT
GNDA
Negative Input Temp ADC PGA
GNDA
Negative Input Temp ADC PGA
Temp ADC Input Mux Configuration #2 Register 6[5:4] = '01' Register 6[M1,M0] = '01' Positive Input VEXC TEMPIN Negative Input Temp ADC PGA
Temp ADC Input Mux Configuration #4 Register 6[5:4] = '11' Register 6[M1,M0] = '11' Positive Input VREF TEMPIN Negative Input Temp ADC PGA
Figure 74.
R1 [1] 0 0 1 1 R0 [0] 0 1 0 1 INTERNAL TEMPERATURE MODE [TEN = 1] 9-Bit + Sign, 0.5C, (3ms) 10-Bit + Sign, 0.25C, (6ms) 11-Bit + Sign, 0.125C, (12ms) 12-Bit + Sign, 0.0625C, (24ms) EXTERNAL SIGNAL MODE [TEN = 0|, EXTERNAL REFERENCE [AREN = 0] 11-Bit + Sign (6ms) 13-Bit + Sign (24ms) 14-Bit + Sign (50 ms) 15-Bit + Sign (100 ms) EXTERNAL SIGNAL MODE [TEN = 0|, INTERNAL REFERENCE [2.048V, AREN = 1] 11-Bit + Sign (8 ms) 13-Bit + Sign (32ms) 14-Bit + Sign (64 ms) 15-Bit + Sign (128 ms)
Table 47. Temp ADC--Resolution (Conversion Tme) Select
80
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
BIT # BIT NAME POR VALUE D15 RFB 0 D14 RFB 0 D13 RFB 0 D12 RFB 0 D11 DLY3 0 D10 DLY2 0 D9 DLY1 0 D8 DLY0 0 D7 OEN7 0 D6 OEN6 0 D5 OEN5 0 D4 OEN4 0 D3 OEN3 0 D2 OEN2 0 D1 OEN1 0 D0 OEN0 0
Bit Descriptions: RFB: Reserved Factory Bit: Set to zero for proper operation
Temp ADC begins conversion after DLY[3:0] x 10ms after valid WRITE to this register. Initial count, DLY[3:0] is decremented every 10ms to zero count and then Temp ADC is enabled. This allows for linearization and excitation analog circuitry to settle before applying temperature compensation.
DLY[3:0]:Temp ADC Delay
OEN[7:0]: Output Enable Counter for One-Wire Interface/VOUT Multiplexed mode.
VOUT is enabled after a valid WRITE to this register. Any non-zero value = VOUT Enable initial count, decremented every 10ms to zero count, and then VOUT is disabled. After VOUT is disabled, a one-second internal timer is set. If serial communication takes place from an outside controller on either the One-Wire interface (PRG pin) or Two-Wire interface, then VOUT will remain disabled as long as the PGA309 is addressed at least once per second.
DLY3 [11] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DLY2 [10] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DLY1 [9] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DLY0 [8] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DECIMAL EQUIVALENT (INITIAL COUNTER VALUE) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TEMP ADC DELAY(1) (ms) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
(1) Temp ADC Delay = Initial Counter Value x 10ms
Table 48. Temp ADC--Delay After VOUT Enable
DIGITAL INPUT OEN7......OEN0 [7......0] (BINARY) 0000 0000 0010 0000 0100 0000 0110 0000 1000 0000 1010 0000 1100 0000 1110 0000 1111 1111
DECIMAL EQUIVALENT (INITIAL COUNTER VALUE) 0 32 64 96 128 160 192 224 255
VOUT ENABLE TIMEOUT(1) (ms) 0 (VOUT disabled) 320 640 960 1280 1600 1920 2240 2550
(2) VOUT Enable Timeout = Initial Counter Value x 10ms
Table 49. Output Enable Counter for One-Wire Interface/VOUT Multiplexed Mode
81
PGA309
www.ti.com SBOS292 - DECEMBER 2003
Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
BIT # BIT NAME POR VALUE D15 X 0 D14 X 0 D13 X 0 D12 X 0 D11 X 0 D10 X 0 D9 X 0 D8 ALM8 X D7 ALM7 X D6 ALM6 X D5 ALM5 X D4 ALM4 X D3 ALM3 X D2 ALM2 X D1 ALM1 X D0 ALM0 X
Bit Descriptions: ALM[8:0]: Fault Monitor Comparator Outputs (1 = Fault Condition)
See Fault Monitor Circuit Section. ALM8 -- A1SAT_HI ALM7 -- A1SAT_LO ALM6 -- A2SAT_HI ALM5 -- A2SAT_LO ALM4 -- A3_VCM ALM3 -- INN_HI ALM2 -- INN_LO ALM1 -- INP_HI ALM0 -- INP_LO
82
PGA309
www.ti.com SBOS292 - DECEMBER 2003
PGA309 EXTERNAL EEPROM--REGISTER CONFIGURATION DATA Checksum1 = 0xFFFF - Sum(Addr0 to Addr12); 16-bit wide, carry over bits are ignored.
EXTERNAL EEPROM ADDRESS (DECIMAL)
0 1 2 3 4 5 00011 (LSBs) Register 3- Reference Control and Linearization Register 3- Reference Control and Linearization Register 4- PGA Coarse Offset and Gain/Output Amp Gain Register 4- PGA Coarse Offset and Gain/Output Amp Gain Register 5- PGA Configuration and Over/UnderScale Limit Register 5- PGA Configuration and Over/UnderScale Limit Register 6- Temp ADC Control Register 6- Temp ADC Control Checksum [LSBs] Checksum [MSBs] Temperature Index Value T0 (LSBs) Temperature Index Value T0 (MSBs) Zero Adjustment DAC Value for T0 and below (LSBs) Zero Adjustment DAC Value for T0 and below (MSBs) Gain Adjustment DAC Value for T0 and below (LSBs) Gain Adjustment DAC Value for T0 and below (MSBs)
PGA309 INTERNAL REGISTER ADDRESS
PGA309 INTERNAL REGISTER DESCRIPTION
DATA (LSBs) (MSBs)
Programmed Flag Value (LSBs)(1) Programmed Flag Value (LSBs)(1) Unused(1) Unused(1) Unused(1) Unused(1)
D7 D15
0 0
D6 D14
1 1
D5 D13
0 0
D4 D12
0 1
D3 D11
1 0
D2 D10
0 1
D1 D9
0 0
D0 D8
1 0
6
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
7
00011 (MSBs)
0
TM1
BG
SD
EXS
EXEN
RS
REN
8
00100 (LSBs)
0
CFG6
CFG2
OS4
OS3
OS2
OS1
OS0
9
00100 (MSBs)
OWD
GO2
GO1
GO0
GI3
GI2
GI1
GI0
10
00101 (LSBs)
0
OUEN
HL2
HL1
HL0
LL2
LL1
LL0
11
00101 (MSBs)
0
0
0
0
EXTEN
INTEN
EXTPOL
INTPOL
12
00110 (LSBs)
RV1
RV0
M1
M0
G1
G0
R1
R0
13
00110 (MSBs)
0
0
ADC2X
ADCS
ISEN
CEN
TEN
AREN
14 15 16 17 18
1CS7 1CS15 T0-D7 T0-D15 Z0-D7
1CS6 1CS14 T0-D6 T0-D14 Z0-D6
1CS5 1CS13 T0-D5 T0-D13 Z0-D5
1CS4 1CS12 T0-D4 T0-D12 Z0-D4
1CS3 1CS11 T0-D3 T0-D11 Z0-D3
1CS2 1CS10 T0-D2 T0-D10 Z0-D2
1CS1 1CS9 T0-D1 T0-D9 Z0-D1
1CS0 1CS8 T0-D0 T0-D8 Z0-D0
19
Z0-D15
Z0-D14
Z0-D13
Z0-D12
Z0-D11
Z0-D10
Z0-D9
Z0-D8
20
G0-D7
G0-D6
G0-D5
G0-D4
G0-D3
G0-D2
G0-D1
G0-D0
21
G0-D15
G0-D14
G0-D13
G0-D12
G0-D11
G0-D10
G0-D9
G0-D8
(1) While these values are not used to configure the PGA309, they are included in Checksum calculations.
Table 50. PGA309 External EEPROM--Register Configuration Data Checksum1
83
PGA309
www.ti.com SBOS292 - DECEMBER 2003
PGA309 EXTERNAL EEPROM--REGISTER CONFIGURATION DATA Checksum2 = 0xFFFF - Sum(Addr16 to AddrZME); 16-bit wide, carry over bits are ignored.
EXTERNAL EEPROM ADDRESS (DECIMAL)
112 113
PGA309 INTERNAL REGISTER ADDRESS
PGA309 INTERNAL REGISTER DESCRIPTION
DATA (LSBs) (MSBs)
Temperature Index Value T16 (LSBs) Temperature Index Value T16 (MSBs)
D7 D15
T16-D7 T16- D15 ZM-D7 ZM- D15 GM-D7 GM- D15 1 0 0 0 GME-D7 GMED15
D6 D14
T16-D6 T16- D14 ZM-D6 ZM- D14 GM-D6 GM- D14 1 1 0 0 GME-D6 GMED14
D5 D13
T16-D5 T16- D13 ZM-D5 ZM- D13 GM-D5 GM- D13 1 1 0 0 GME-D5 GMED13
D4 D12
T16-D4 T16- D12 ZM-D4 ZM- D12 GM-D4 GM- D12 1 1 0 0 GME-D4 GMED12
D3 D11
T16-D3 T16- D11 ZM-D3 ZM- D11 GM-D3 GM- D11 1 1 0 0 GME-D3 GMED11
D2 D10
T16-D2 T16D10
D1 D9
T16-D1 T16-D9
D0 D8
T16-D0 T16-D8
114
Zero Adjustment DAC Scale Factor for T16 and below (LSBs) Zero Adjustment DAC Scale Factor for T16 and below (MSBs) Gain Adjustment DAC Scale Factor for T16 and below (LSBs) Gain Adjustment DAC Scale Factor for T16 and below (LSBs) TEND (End of Look-up Table) LSBs(1) TEND (End of Look-up Table) MSBs(1) ZME (End of Look-up Table) LSBs(1) ZME (End of Look-up Table) MSBs(1) GME (End of Look-up Table)-Checksum2 LSBs GME (End of Look-up Table)-Checksum2 MSBs
ZM-D2 ZM- D10 GM-D2 GM- D10 1 1 0 0 GME-D2 GMED10
ZM-D1
ZM-D0
115
ZM-D9
ZM-D8
116
GM-D1
GM-D0
117 118 119 120 121 122
GM-D9 1 1 0 0 GME-D1
GM-D8 1 1 0 0 GME-D0
123
GME-D9
GME-D8
(1) While these values are not used to configure the PGA309, they are included in Checksum calculations.
Table 51. PGA309 External EEPROM--Register Configuration Data Checksum2
84
PGA309
www.ti.com SBOS292 - DECEMBER 2003
DETAILED BLOCK DIAGRAM
VS A REFIN /REFO U T VS A Linearization and VE X C Gain Adjust
X0.166
V SD VS D VS D POR
VS A VF B X0.83 VR E F Internal Set (2.5V or 4.096V) X0.52 VR E F
VE X C VE X C
VE X C Enable
7- + Sign Bit DAC
VS A
X0.124
Bandgap Reference
VR E F INT Temp IT E M P Enable TEMPIN TEMPI N VR EF VE X C VO UT Control Registers Temp ADC, PGA (x1, x2, x4, x8) Temp ADC Input Mux Select PGA Gain Select (1 of 8) Range of 4 to 128 (with PGA Diff Amp Gain = 4) Input Mux Control Coarse Offset Adjust Temp Select Source Alarm Register Interface and Control Circuitry Temp ADC Input Mux xG Temp ADC Internal REF Temp ADC Ref Mux VE X C VS A VR E F T
1 5-B it + S ign T em p A D C
VR E F Internal Set (2.5V or 4.096V)
Temp ADC REF Select
RS E T
Digital Controls SDA SCL
Offset TC Adjust and Scan PC Adjust Look- Logic with Interpolation Algorithm Up Fine Offset Adjust 16- Bit DAC (Zero DAC) Auto Zero A2 R Front End PGA Output Over- Scale Limit 4R PRG Fine Gain Adjust (16-Bit)
VR E F
4-Bit + S ign D AC
VR E F
V IN 2
VI N P
RF
PGA Diff Amp RG RF Auto Zero R A3
VR E F
3- Bit DAC V F B VO U T
Front End PGA R
Output Amplifier Scale Limiter VO U T
V IN 1 Input Mux
V IN N
Auto Zero
A1
INT/EXT FB Select Fault Monitor Circuit Alarm Register Inputs RFO VF B
Output Gain Select ( 1 of 7) Range of 2 to 9 Test Test Logic
VR E F RGO
3- Bit DAC
Under- Scale Limit PGA309 GNDA GNDD
VS J
Figure 75. Detailed Block Diagram
85
MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

▲Up To Search▲

Price & Availability of PGA309

	To Download PGA309 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .